ring and johnson shift register counters are definition shift register counter example | what is define shift register counters meaning ?
Shift Register Counters
A shift register counter is basically a shift register with the serial output connected back to the serial input in order to produce special sequences. these devices are often classified as counters becaues they exhibit a specified sequence of states. two of the most common types of shift register counters are the johnson counter and the ring counter.
The johnson counter In a johnson counter the complement of the output of the last flip-flop is connected back to the D input of the first flip-flop (it can be implemented with S-R or J-K flip-flop as well). this feedback arrangement produces a unique sequence of states as shown as for a four-bit device.
In general, an n stage johnson counter will produce a modulus of 2n, where n is the number of stages in the counter. Diagrams of the timing operations of the four bit counter shown in figure.
The Ring Counter
The ring counter utilizes one flip-flop for each state in its sequence, and it is therefore wasteful of flip-flop. it does have the advantage that decoding is not required for decimal conversion.
- The circuit given below is a
(a) J-K flip-flop
(b) johnson’s counter
(c) RS latch
(d) None of these
- Consider the circuit shown in figure
The expression for the next state Q+ is
(b) x * Q
(d) x * Q
- Which one of the following circuit converts an RS flip-flop to T-flip-flop?
- Input shown below is applied to T-flip-flop. the output waveform will be
- The initial contents of the 4-bit serial-in-parallel out shift register, register shown in figure is 0110. After three clock pulses are applied, the content of shift register will be
- The counter shown in figure counter from
(a) 000 to 111
(b) 111 to 000
(c) 100 to 000
(d) 000 to 100
- The three-stage johnson counter as shown in figure. this circuit is clocked at a constant frequency of fc from the stating state of Q2Q1Q0 = 101, The frequency of output Q2Q1Q0 Will be
- For the circuit shown, the counter state (Q1, Q0) follow the sequence
(a) 00, 01, 10, 11, 00
(b) 01, 10, 00, 01
(c) 00, 01, 11, 00, 01
(d) 10, 11, 00, 10
- A 4-bit right shift register is initialized to value 1000 for (Q3, Q2, Q1, Q0). The D input is derived from Q0, Q2 and Q3 through two XOR gates as shown in figure. the pattern 1000 will appear at
(a) 6th pulse
(b) 4th pulse
(c) 3rd pulse
(d) 7th pulse
- The initial state of MOD-16 down counter is 0110. what will it be after 37 clock pulses?
- A certain J-K flip-flop has tnd = 12 ns. the largest MOD ripple counter that can be constructed from these FFs and still operate upto 10 MHz is
- Why is the frequency of the output of the eight FF when the input clock frequency is 512 KHz.
(a) 16 KHz
(b) 4 KHz
(c) 2 KHz
(d) 8 KHz
- if tp – duration of the clock pulse
t – propagation delay
T – clock period
then to avoid race-around condition occurring with j-k flip-flop.
(a) tp = t = T
(b) tp – t = T
(c) tp < t = T
(d) tp < t = T
- Asynchronous counter shown in figure below is
(a) MOD-21 counter
(b) MOD-22 counter
(c) MOD-20 counter
(d) MOD-19 counter
- What memory address range is not represented by chip #1 and chip #2 in the figure? A0 to A15 in this figure are the address lines and CS means chip select.
(c) F900 -FAFF
- In FF clocking
(a) hold time is greater than set up time
(b) set up time is greater than hold time
(c) hold time is before edge triigering
(d) set up time is after edge triggering
- Which of the follownig circuit converts a j-k flip-flop to a T flip-flop?
- In a j-k flip-flop, we have j-q and k = 1 in the figure. assuming the flip-flop was initially cleared and then clocked for 6 pulses, the sequence at the Q output will be
- Minimum number of j-k flip-flops needed to constructed a BCD counter is
- The number of unused states in a 4-bit johnson counter is
Answers with Solutions
Given circuit represents RS latch.
Q+ = xQ + xQ
Q+ = x * Q
The conversion table for converting RS flip-flop to T flip-flop.
Thus, the logic diagram of T flip-flop using S-R flip-flop is shown below.
truth table of T type flip-flop
At pulse input 1 * 0 = 1
So, contents 1011.
at pulse 2 input 1 * 1 = 0
so, contente are 0101.
at pulses 3 input 0 * 1 = 1
so, contents are 1010.
it is a down counter because the inverted flip-flop output frive the clock inputs. the NAND gate will clear flip-flop s A and B when the count tries to recycle 111. this will produce as result of 100. thus the counting sequence will be 100, 011, 011, 010, 001, 000, 100 etc.
this counter is turncated counter sequence will be
thus, sequence will be from 100 to 000.
From the table, we can conclude that 101 repeat after every two cycle hence, frequency will be fc/2
output states of the counter
so, sequence will be 01, 10, 00, 01.
hence, in the sixth clock pulse we get 1 0 0 0 at output.
This is a MOD-16 down counter and its initial state is 0110. the state after 37th clock will be
let suppose that there is n flip-flops are connected. so, frequency
f = 1/ n.td
10 x 106 = 1/ n x 12 x 10-9
n = 8
so, 28 = 256 MOD ripple counter can be constructed with the help of it.
the output frequency eight flip-flop
= 1/28 x input frequency
= 1/28 x 512
f8 = 2 KHz
for avoiding race around condition pulse width should be smaller than the delay and this should be smaller than the time period of the pulse.
this counter will be reset at 1 0 1 0 0 …..(20). so, the asynchronous counter represents MOD -20 counter.
F800 -F9FF cannot be the memory range of chip #1 and chil #2.
in flip-flop clocking set-up time is kept greater than hold time.
for converting j-k flip-flop into T flip-flop making the following table :
Now, using k-map simplification :