synchronous sequential circuits and asynchronous sequential circuits notes definition examples

synchronous sequential circuits that uses clock are called synchronous sequential circuits and asynchronous sequential circuits notes definition examples . difference between synchronous sequential circuits and asynchronous sequential circuits . the behaviour of synchronous sequential circuit can be predicted by defining the signals at
Sequential logic Circuits
Sequential circuits   Sequential circuit is a combination of a combinational circuit and a memory elements connected in feedback path. the memory elements can store binary information.
Sequential Circuit
The Sequential circuit receives binary information from external inputs. the inputs, together with the present state of the memory elements, determine the binary value of the input. the block diagram of sequential circuit shown :
Thus a sequential circuit is specified by a time sequence of inputs, outputs states. A sequential circuit is of two main types depending on the timing of their signals.
Synchronous Sequential Circuit
Synchronous sequential circuit is a system whose behaviour can be defined from the knowledge of its signals at discrete instant of time.
Asynchronous Sequential Circuit
This circuit depends upon the order in which its inputs signals change and can be affected at any instant of time. the memory elements commonly used in asynchronous sequential circuits are time delay devices.
Clocked Sequential Circuit
Synchronous sequential circuits that use clock pulses in the inputs of memory elements are called clocked sequential circuits.
The memory elements used in clocked sequential circuits are called flip-flops. flip-flops are binary cells capable of storing one bit of information. a flip-flop circuit has two outputs, one is the normal value and other its complement value.
NAND Gate latch
The most basic flip-flop circuit can be constructed from either two NAND gates or two NOR gates. the NAND gate version is called NAND gate latch. the NAND latch is shown in figure.
The two NAND gates are cross coupled so that the cross coupled connection from the outputs of one gate to the input of the other gate constitutes a feedback path.
NOR Gate Latch
Two cross coupled NOR gates can be connected to operate as a NOR latch. it is similar to the NAND latch except that the two outputs Q and Q have reversed positions. the NOR gate latch with its truth table is shown in figure.
The latch has two useful states. when output Q = 1 and Q = 0, the latch is said to be in the set state. when Q = 0 and Q = 1, it is in the reset. outputs Q and Q are normally the complement of each other. However when both inputs are equal to 1 at the same time a condition in which both outputs are equal to 0 (rather than be mutually complementary) occurs. if both inputs are switched to 0 simultaneously, the device will enter an unpredictable or undefined state or a metasteble state. consequently, in practical applications, setting both inputs to 1 is forbidden.
Clocked Flip-Flops
Flips-fiops are synchronous bistable devices. the term synchronous means that the output changes state only at a specified point on a triggering input called the clock.
The term edge triggered means that the flip-flop changes state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse and is sensitive to its inputs only this transition of the clock. The simplest form of data storage is the set-reset (SR) flip-flop.

  1. SR Flip-Flop (Set-Reset)

The simple SR flip flop will be set or reset at any time by changing the inputs S and R. but in clocked SR flip-flop set or reset is done with the help of clock pulse. the circuit diagram of clocked SR flip-flop is shown in figure.
When the clock is absent (CLK = 0) the outputs of both the gates G3 and G4 are 1 and there is no change in the outputs of G1 and G2 When the CLK is present (CLK = 1 ) the outputs of G3 and G4 are the function of inputs S and R.

  1. When S = 0 and R = 0

then output of G3 and G4 are 1, 1 and output of G1 and G2 are unchanged.

  1. When S = 0 and R = 1

then output of G3 will be 1 and G3 will be 0. and flip-flop is reset.

  1. When S = 1 and R = 0

then output of G3 is zero and output of G4 is 1. and output will be set.

  1. When S = 1 and R = 1

then output of G3 and G4 are 0. and the output is undefined because outputs of G1 and G2 try to become 1.
J-K Flip-Flop
The limitation of SR flip-flop is overcome in J-K flip-flop. the logic diagram of J-K flip-flop is shown in figure
D Flip-Flop
D-flip flop is also known as delay flip-flop. the D -Flip-flop is obtained from the J-K flip-flop by connecting a NOT gate between J and K input of the J-K flip-flops as shown in figure
T Flip-flop
The T flip-flop is a single input version of the J-K flip-flop. in this both the inputs are tied together, regardless of the present state of the flip-flop, output of flip-flop is complemented, when the clock pulse occurs while input T is high. the designation T comes from the ability of flip-flop to toggle or change state.
Figure below shows the truth table and logic diagram of a T flip-flop.
Race-Around Condition
For Jn = 1 and KN = 1, the j-k flip-flop acts as a toggle switch consider the input JN = 1 and KN = 1 and output Q = 0; after the propagation delay t of flip-flop the output will change from 0 to 1. since, in a J-K flip-flop, output is connected to inputs, this output acts as input and after the next delay t, the output will change from 1 to 0. this process is continued and at the end of the applied clock pulse, the output is uncertain. this situation is known as the race-around condition.
The race-around condition is major problem in J-K flip-flop. this uncertainty of output can be avoided, if the delay of the flip-flop is increased. delay of flip-flop (t) must be greater than the duration of clock pulse (t) or the duration of the applied clock pulse (t) gets reduced and it becomes less than the delay of flip-flop (t).
The most practical solution to aviod the problem of race-around condition is to use the J-K flip-flop in master and slave mode.
Master-Slave Flip-Flop
A master-slave flip-flop basically contains two flip-flops a master and a slave. a master-slave flip-flop can be constructed using two J-K flip-flops connected serially. the first flip-flop serves as master and second as a slave and the overall circuit is referred to as a master-slave flip-flop. the first flip is driven by positive edge of clock pulse, the second flip-flop is driven by the negative edge of clock pulse.
A counter is a sequential logic circuit capable of counting the number of clock pulses arriving at its clock input. this count sequence may be ascending, descending or non-sequence. a specified sequence of states appear at the counter output. each count of the counter is called the state of counter.
MOD Number
The number of states through which the counter passes before returning to the starting or initial state. in general, if N flip-flop are connected in above arrangement, the counter will have 2n different states and so it is a MOD -2N counter. it would be capable of counting upto, 2n – 1 before returning to zero state.
MOD number = 2n
MOD number indicates the frequency division obtained from the last flip-flop.
For example A 4-bit counter has four flip-flops, each representing one binary digit (bit) and so it is called a MOD -24 or MOD -16 counter. it can count 15 (24-1). it can also be used to divide the input pulse frequency by a facter 16.
It we use N flip-flops, then the output frequency of last flip-flop is equal to 1/2n of the input frequency.
output frequency = 1/2n x input frequency.
Classification of Counters
Counter circuit is a combination of flip-flops and combinational elements. depending upon the manner in which flip-flops are triggered, counters can be classified into two major groups
(a) Asynchronous counter (Ripple counter)
(b) Synchronous counter
(a) Asynchronous counter (Ripple counter)
In asynchronous counter the first flip-flop is clocked by the external clock pulse and then each successive flip-flop is clocked by the output of previous flip-flop. thus, flip-flops are not clocked simultaneously in asynchronos counter.
A three-bit asynchronous binary counter  Figure shows a three-bit asynchronous counter. the (CLK) clock line is connected to the clock input (c) of only the first stage, FFA. the second stage, FFB is triggered by QA output of FFA and the third state, FFC is triggered by QB output of FFB. therefore, the two flip-flop are never simultaneously triggered, which results in asynchronous counter operation.
Example 1. A four- sate asynchronous binary counter is shown in figure. each flip-flop is negative edge-triggered and has a propagation delay of 10 nano seconds (ns). draw a timing diagram showing the Q output of each stage, and determine the total delay time from the triggering edge of a clock pulse until a corresponding change can occur in the state of Qd.
Sol. The timing diagram with delays omitted is as shown in figure. to determine the total delay, the effect of CLK8 or CLK16 must propagate through four flip-flops before QD changes.
tp = 4 x 10 ns = 40 ns, total delay
Asynchronous Decade Counters
Maximum possible number of states (maximum modulus) of a counter is 2n, where n is the number of flip-flops in the counter. counters can also be designed to have a number of states in their sequence that is less than 2n. the resulting sequence is called a truncated sequence. one common modulus for counters with truncated sequence is ten. counters with ten states in their sequence are called decade counters. A decade counter with a count sequence of 0 (0000) through 9 (1001) is a BCD decade counter because its ten-state sequence is the BCD code.
To obtain a truncated sequence, it is necessary to force the counter to recycle before going through all of its normal states. for example, the BCD decade counter must recycle back to the 0000 state after the 1001 state.
A decade counter requires four flip-flop (three flip-flops are insufficient because 23 = 8). we will now take a four-bit asynchronous counter such as the one in fig. (a) and modify its sequence in order to underatand the principle of truncated counters. one method of achieving this recycling after count of 9 (1001) is to decode count 1010 (1010) with a NAND gate and counect the output of the NAND gate to the clear (CLR) inputs of the flip-flops, as shown is fig. (b).
Example 2. Show, how an asynchronous counter can be implemented with a modulus of twelve with a straight binary sequence from 0000 through 1011 ?.
Solution  Since, three flip-flops can produce a maximum of eight states, four flip-flop are required to produce any modulus greater than eight but less than or equal to sixteen.
When the counter gets to its last state, 1011, it must recycle back to 0000 rather than going to its normal next state of 1100, as illustrated in the sequence chart below.
3-Bit ripple UP/Down Counter
The three bit ripple up/down counter can count the sequence in both up and down direction.
For up direction M = 1 and sequence
(b) Synchronous Counters
The term synchronous as applied to counter operation means that the counter is clocked such that each flip-flop in the counter is triggered at the same time. this is accomplished by connecting the clock line to each stage of the counter.
Synchronous Counter Design
In a synchronous counter the clock pulse is given simultaneously to all the flip-flops and the transition at the output is in synchronism with the clock inputs. the design procedure of synchronous counter is as follows

  1. Find the number of flip-flops required.

For a modulus-M counter, the number of flip-flop required is n, such that M < 2N

  1. It is noted that n-bit counter is also known as a modulo 2n counter.
  2. Write the given sequence in the form of present state and next state (QN and Qn + 1).
  3. With the help of excitation table, find the inputs of flip-flop for the given transition.
  4. Prepare K-map for each input of flip-flops in terms of output of the flip-flops and simplify.
  5. Connect the inputs to the flip-flops as per the simplified boolean equations.

Example 3.  Design a 3-bit synchronous counter using J-K flip-flops.
Sol. for a 3-bit counter, three flip-flops are required n = 3.
the sequence in the form of present state and next state with the excitation table of J-K flip-flop is given
The 3-bit synchronous counter using J-K flip-flop is shown below
State sequence for a three-stage binary counter.
Example 4. Design a MOD -5 synchronous counter using T – flip-flops.
Sol.  for a MOD -M coumter, the number of flip-flops required is n.
M < 2N or 5 < 2N or n = 3
The sequence in the form of present state and next state with the excitation table of T flip-flop is
The MOD-5 synchronous counter using T flip-flop is shown below
UP/DOWN Synchronous Counter
An UP/DOWN counter is one that is capable of progressing in either direction through a certain sequence. it is also sometimes called bidirectional counter.
The UP/DOWN operation of the counter is controlled by UP/DOWN signal, when the signal is high, counter goes through up sequence (0,1,2,3 ……,n) and when the UP/DOWN signal is low then the signal follows reverse sequence (n, n -1, n-2…….,2,1,0).
Let us design a 3-bitbnup-down synchronous counter, using T flip-flop. the excitation table for 3-bit UP/DOWN Synchronous counter.
Registers are commonly used for the temporary storage of data within a digital system. registers are implemented with flip-flops or other storage devices. the shift capability of a register permits the movement of data from stage to stage within the register or into or out of the register upon application of clock pulses. figure shows symbolically the types of data movement in shift register operations. the block represents any arbitrary four-bit register, and the arrow indicates the direction and type of data movement.
Classiflcation of Shift Registers
A register is basically a set of flip-flops logically connected to perform various functions. the following classification given below is based on the operation and mode of input and output.

  1. Classification based on the mode of input and output
  2. Serial in serial out shift register (SISO)
  3. Serial in parallel out shift register (SIPO)
  4. Paralled in serial out shift register (PISO)
  5. Parallel in parallel out shift register (PIPO)
  6. Universal shift register.

II Classification based on the direction of data movement

  1. Shift left register
  2. Shift right register
  3. Bidirectional shift register

Serial in serial out shift register
The serial in serial out shift register accepts the data serially on a single input line. it also produces the stored information on its output in serial form. Data can be shifted from left side or right side based on this the register is called shift left or shift right register. the figure shown serial in serial out shift register
The working of shift register can be explained as
if we want to get the data out of the register, they must shifted out serially and taken off the QD output.
Flip-flop Conversions
It is possible to convert one flip-flop into another with some additional circuit. the following steps are used to conversion :
Step 1  Write the excitation table.
Step 2 Simplify the excitation table using K-map
Step 3 Draw the desired logic diagram.
Example 5. Show the states of the five-bit register in figure for the specified data input clock waveforms. assume that the register is initially cleared (all 0’s).
Serial in Parallel out shift registers
Data bits are entered into this type of register in the same manner as in serial in serial out shift register. the difference is the way in which the data bits are taken out of the register, in the parallel output register, the output of each stage is available.
Example 6. Show the states of the four-bit register for the data input and clock waveforms in figure. the register initially contains all 1’s.
Sol. The register contains 0110 after four clock pulses. see figure.
Parallel in serial out shift registers For a register with parallel data inputs, the bits are entered simultaneously into their respective stages on parallel lines rather than on a bit bit-by-bit basis on one line as with serial data inputs.
Example 7. Show the data-output waveform for a four-bit register with the parallel input data and clock waveform given in figure.
Sol. on clock pulse 1, the parallel data (1010) are loaded intp the register, making QD a 0. on clock pulse 2, the 1 from QC is shifted onto QD, on clock pulse 3, the 0 is shifted onto QD on clock pulse 4,the next 1 is shifted onto QD and on clock pulse 5 and 6, all data bits have been shifted out and only 0s remain in the register because on new data have been entered.
Parallel in Parallel out Register
in parallel in parallel out registers, the bits are entered simultaneously into their respective stages on parallel line and the bit appear on the parallel outputs.
When the SHIFT/LOAD (SH/LD) input is low, the data on the parallel inputs are entered synchronously on the positive transition of the clock. when the SH/LD input is high, stored data will shift right (QA TO QD ) synchronously with the clock. J and K are the serial data inputs to the first stage of the register (QA): QD can be used for serial output data. the active-low clear is asynchronous.
Bidirectional Shift Registers
A bidirectional shift registers is one in which the data can be shifted either left or right.

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