the ripple counter shown in the given figure 2 works as a or in the modulo 6 ripple counter shown in the figure the output of the 2 input  ?
Unit Exercise – 2

1. A computer has the following negative number stored in binary form as shown. the wrongly stored number is

(a) -37 as 1101 1011
(b) -89 as 1010 0111
(c) -48 as 1110 1000
(d) -32 as 1110 0000

1. if X = 1 in the logic equation

e (X + Z{Y +(Z + Y)}] [X + Z(X + Y)] = 1, Then
(a) Y = Z
(b) Y = Z
(c) Z = 1
(d) Z = 0

1. If the input x3, x2, x1, xo to the ROM in figure are 8-4-2-1 BCD number, then the output Y3Y2Y1Y0 are

(a) gray code number
(b) 2-4-2-1 BCD number
(c) excess 3 code number
(d) none of the above

1. In figure the j and k inputs of all the four flip-flops are made high. the frequency of the signal at output y is

(a) 0.833 KHz
(b) 1.0 kHz
(c) 0.91 kHz
(d) 0.77 kHz

1. Consider the CMOS circuit shown in figure. it acts as a

(a) negative NAND
(b) positive NAND
(c) negative NOR
(d) positive NOR

1. 11001, 1001 and 111001 correspond to the 2’s complement representation of which one of the following sets of number?

(a) 25, 9 and 57 respectively
(b) – 6, -6 and -6 respectively
(c) -7, -7 and -7 respectively
(d) -25, -9 and -57 respectively

1. The Boolean expression AC + BC is equivalent to

(a) AC + BC + AC
(b) BC + AC + BC + ACB
(c) AC + BC + BC + ABC
(d) ABC + ABC + ABC + ABC

1. Expression A + AB + A BC + ABCD + ABCDE would be simplified to

(a) A + AB + CD + E
(b) A + B + CDE
(c) A + BC + CD + DE
(d) A + B + C + D + E

1. For the circuit shown in the following figure I0 – I3 are inputs to the 4 : 1 multiplexer R (MSB) and S are control bits

the output Z can be represented by
(a) PQ + PQS + QRS
(b) PQ + PQR + PQS
(c) PQR + PQR + PQRS + QRS
(d) PQR + PQRS + PQ RS + QRS

1. A 4-bit right shift register is initialized to value 1000 for (Q3, Q2, Q1, Q0). The D input is derived from Q0, Q2 and Q3 through two XOR gates as shown in figure. the pattern 1000 will appear at

(a) 3rd pulse
(b) 7th pulse
(c) 6th pulse
(d) 4th pulse

1. A certain logic family has the following voltage parameters;

VIH(MIN) = 3.5 V, VIL(MAX) = 1.0 V,  VOH(MIN) = 4.9 V and  VOL(MAX) = 0.1 V. The largest positive-going and negative-going spike, that can be tolerate, is respectively
(a) 1.4 v, 0.9 v
(b) 0.9 v, 1.4 v
(c) 3.9 v, 3.4 v
(d) none of these

1. The two numbers represented in signed 2’s complement form are p = 11101101 and Q =11100110. If Q is subtracted from p, the value obtained in signed 2’s complement form is

(a) 100000111
(b) 00000111
(c) 11111001
(d) 111111001

1. X = ?

(a) AB
(b) AB
(c) AB
(d) 0

1. The circuit shown in figure converts

(a) BCD to binary code
(b) binary to excess-3 code
(c) excess-3 to gray code
(d) gray to binary code

1. In figure, the LED

(a) emits light when both S1 and S2 are closed
(b) emits light when both S1 and S2 are open
(c) emits light when only S1 or S2 is closed
(d) does not emit light, irrespective of the switch positions

1. The CMOS circuit shown in figure, implements

(a) AB + CD + E
(b) (A + B) (C + D) E
(c) AB + CD + E
(d) (A + B) (C + D) E

1. 7-bit hamming code groups consisting of 4 formation bits and 3 parity bits is transmitted. the group 1101100 is received in which at most a single has occurred. the transmitted code is

(a) 1111100
(b) 1100100
(c) 1001100
(d) 1101000

1. In the following circuit, X is gives by

(a) X = ABC + ABC + ABC + ABC
(b) X = ABC + ABC + ABC + ABC
(c) X = AB + BC + AC
(d) X = AB + BC + AC

1. The mod-number of the asynchronous counter shown in figure is

(a) 24
(b) 48
(c) 25
(d) 36

1. In the modulo-6 ripple counter shown in figure, the output of the 2-input gate is used to clear the j-k flip-flops.

The 2-input gate is
(a) a NAND gate
(b) a NOR gate
(c) an OR gate
(d) an AND gate

1. In the DRAM cell in figure the VT of the n-MOSFET is 1 v. for the following three combinations of WL and BL voltages.

(a) 5 V; 3 V; 7 V
(b) 4 V; 3 V; 4 V
(c) 5 V; 5 V; 5 V
(d) 4 V; 4 V; 4 V

1. Consider the signed binary number A = 01000110 and B = 11010011, where B is in 2’s complement and MSB is the sign bit. in list I operation is given and in list II resultant binary number is given, match them and find the correct answer using the codes given below the lists.

List I                                                                   List II

1. A + B 1. 1 0 0 0 1 1 0 1
2. A – B 2. 1 1 1 0 0 1 1 1
3. B – A 3. 0 1 1 1 0 0 1 1
4. – A – B 4. 1 0 0 0 1 1 1 0
5. 0 0 0 1 1 0 1 0
6. 0 0 0 1 1 0 0 1
7. 0 1 0 1 1 0 1 1

Codes
P                      Q                           R                  S
(a)          5                      7                             4                  2
(b)          6                       3                           1                    2
(c)         6                        7                            1                    3
(d)         5                        3                            4                    2

1. Consider the signed binary number A = 01010110 and B = 11101100 where, B is the 1’s complement and MSB is the sign bit. in list I opertion is given, and in list II resultant binary number is given match them and find the correct answer using the codes below the lists.

List I                                                           List II

1. A + B 1. 0 1 0 0 0 0 1 1
2. B – A 2. 0 1 1 0 1 0 0 1
3. A – B 3. 0 1 0 0 0 0 1 0
4. – A – B 4. 1 0 0 1 0 1 0 1
5. 1 0 1 1 1 1 0 0
6. 1 0 0 1 0 1 1 0
7. 1 0 1 1 1 1 0 1
8. 0 1 1 0 1 0 1 0

Codes
P                     Q                  R                 S
(a)         3                       4                  2                  5
(b)         3                        6                  8                  7
(c)         1                         4                  8                  7
(d)         1                        6                   2                  5

1. The minimum number of 2 to 1 multiplexers equired to realize a 4 to 1 multiplexer is

(a) 1
(b) 2
(c) 3
(d) 4

1. An ECL gate exhibits the following characteristics VOH(MIN) = – 0.8 V, VOL(MAX) = 2.0 V, and VNL = VNH = 0.5 V. the values of VIH(MIN) and VIL(MAX) would be respectively,

(a) -0.3 v, 2.5 v
(b) -1.3 v, -1.5 v
(c) 1.3 v, -1.5 v
(d) 0.3 v, 2.5 v

1. 11001, 1001 and 111001 correspond to the 2’s complement representation of the following set of numbers

(a) 25, 9 and 57 respectively
(b) -6, -6 and -6 respectively
(c) -7, -7 and -7 respectively
(d) -25, -9 and -57 respectively

1. A new binary coded pentary (BCP) number system is proposed in which every digit of a base-5 number is represented by its corresponding 3-bit binary code. for example, the base-5 number 24 will be represented by its BCP code 010100. in this numbering system, the BCP code 100010011001 corresponds to the following number in base-5 system

(a) 423
(b) 1324
(c) 2201
(d) 4231

1. In the circuit shown in figure A is a parallel-in parallel-out 4-bit register which loads at the rising edge of the clock C. the input lines are connected to a 40-bit bus, W. its output acts as the input to a 16.4 ROM whose output is floating when the enable input E is 0. A partial table of the contents of the ROM is as follows :

The clock to the register is shown and the data on the W bus at time T1 is 0110. the data on the bus at time t2 is
(a) 1111
(b) 1011
(c) 1000
(d) 0010

1. Z = ?

(a) ABC
(b) A B C
(c) 0
(d) ABC

1. The logic function implemented by the following circuit at the terminal Out is

(a) P NOT Q
(b) P NAND Q
(c) P OR Q
(d) P NAND Q

1. A signed integer has been stored in a byte using 2’s complement format. we wish to store the same integer in 16-bit word. we should copy the original byte to the less significant byte of the word and fill the more significant byte with

(a) 0
(b) 1
(c) equal to the MSB of the original byte
(d) complement of the MSB of the original byte

1. What are the minimum number of 2 to 1 multiplexers required to generate a 2 input AND gate and a 2 input Ex-OR gate ?

(a) 1 and 2
(b) 1 and 3
(c) 1 and 1
(d) 2 and 2

1. The DTL, TTL, ECL, and CMOS families of digital ICs are compared in the following 4 columns P                      Q                     R                           S

Fan-out is minimum    DTL                     DTL                   TTL                    CMOS
Power consumption is  TTL                  CMOS                 ECL                    DTL
Propagation delay is    CMOS               ECL                     TTL                   TTL
minimum
The correct column is
(a) P
(b) Q
(c) R
(d) S

1. What is the value of Z?

(a) ABC
(b) AB(C + B)
(c) ABC
(d) AB(C + B)

1. The digital block in figure is realized using two positive edge triggered D flip-flops Assume that for t < to, Q1 = Q2 = 0. The circuit in the digital block given by

(a) fig (A)
(b) fig. (B)
(c) fig. (C)
(d) fig. (D)

1. The boolean expression for the truth table shown below is

(a) B(A + C) (A + C)
(b) B (A + C) (A + C)
(c) B (A + C) (A + C)
(d) B (A + C) (A + C)

1. The boolean function realized by the logic circuit shown is

(a) f = m(0,1,3,5,9,10,14)
(b) f = m (2,3,5,7,8,12,13)
(c) f = m (1,2,4,5,11,14,15)
(d) f = m (2,3,5,7,8,9,12)

1. Two D flip-flops as shows below are to be connected as a synchronous counter that goes through the following Q1Q0 sequence

00 – 01 – 11 – 10 – 00
The inputs D6 and D1 respectively, should be connected as
(a) Q1 and QO
(b) Q0 and Q1
(c) Q1Q0 and Q1QO
(d) Q1QO and Q1QO

1. For the 4-bit DAC shown in figure the output voltage VO is

(a) 10 v
(b) 5 v
(c) 4 v
(d) 8 v

1. if the functions w, x, y and z are as follows :

W = R + PQ + RS
X = PQRS + PQRS + PQRS
Y = RS + PR + PQ + PQ
Z = R + S + PQ + PQR + PQS
Then,
(a) w = z, x = z
(b) w = z, x = y
(c) w = y
(d) w = y = z

1. The k-map for a boolean functions is shown in figure. the number of essential prime implicants for this function is

(a) 3
(b) 4
(c) 5
(d) 6

1. What memory address range is not represented by chip # 1 and chip # 2 in figure A0 to A15 is the figure are the address lines and CS means chip select

(a) 0100 – 02 FF
(b) 1500 – 16 FF
(c) F900 – FAFF
(d) F800 – F9FF

1. The circuit shown in figure is a 4-bit DAC. the input bits 0 and 1 are represented by 0 and 5 v respectively. the op-amp is ideal but all the resistances and the 5 v inputs have tolerance of +10% the simplification (rounded to the nearest multiple of 5%) for the tolerance of the DAC is

(a) + 35%
(b) + 20%
(c) +10%
(d) + 5%

1. The boolean expression Y = ABCD + ABCD + ABCD + ABCD can be minimized to

(a) Y = ABCD + ABC + ACD
(b) Y = ABCD + BCD + ABCD
(c) Y = ABCD + BCD + ABCD
(d) Y = ABCD + BCD + ABCD

1. The boolean expression AC + BC is equivalent to

(a) AC + BC + AC
(b) BC + AC + BC + ACB
(c) AC + BC + BC + ABC
(d) ABC + ABC + ABC + ABC

1. In the circuit shown in figure is PIPO 4-bit register, which loads at the rising edge of the clock. the input lines are connected to a 4-bit bus. its output acts as the input to a 16 x 4 ROM whose output is floating when the enable input E is 0. a partial table of the contents of the ROM is as follows :

The data on the bus at time t2 is
(a) 1 1 1 1
(b) 1 0 1 1
(c) 1 0 0 0
(d) 0 0 1 0

1. The circuit in figure has two CMOS NOR gates. this circuit functions as a

(a) flip-flop
(b) schmitt trigger
(c) monostable multivibrator
(d) astable multivibrator

1. The boolean expression (x + y) (x + y) (x + y) is equivalent

(a) xy
(b) xy
(c) xy
(d) xy

1. f = ?

(a) wxyz + wxyz + xy + yz
(b) wxyz + wxyz + xy + yz
(c) wxyz + wxyz + yz + zx
(d) wxyz + wxyz + gz + zx

1. The three-stage johnson counter as shown in figure is clocked at a constant frequency of fc from the starting state of Q2Q1Q0 = 101. the frequency of output Q2Q1QO will be

(a) fc/4
(b) fc/8
(c) fc/2
(d) fc/6

1. What are the counting stages (Q1, Q2) for the counter shown in the figure below?

(a) 11, 10, 00, 1, 10…………
(b) 01, 10, 11, 00, 01………
(c) 00, 11, 01, 10, 00,………
(d) 01, 10, 00, 01, 10……….

1. A digital voltmeter uses a 10 MHz clock and has a voltage controlled generator which provides a width of 10 us per volt of unit signal. 10 v of input signal would correspond to a pulse count of

(a) 1500
(b) 750
(c) 1000
(d) 500

1. Z = ?

(a) A + B + C
(b) ABC
(c) AB + BC + AC
(d) All of these

1. The 4-to-1 multiplexer shown in figure implements the boolean expression

f(w,x,y,z) = m(4,5,7,8,10,12,15)
The input to I1 and I3 will be
(a) yz, y + z
(b) y + z, y * z
(c) y + z, y * z
(d) x + y, y * z

1. The digital block in figure realized using two positive edge triggered D flip-flop. assume that for t < t0, Q1 = Q2 = 0.

The circuit in the digital block is given by

1. A 4-bit ripple counter and a 4-bit synchronous counter are made using flip-flops having propagation delay of 10 ns each. if the worst case delay in the ripple counter and the syschronous counter be R and S respectively, then

(a) R = 10 ns, S = 40 us
(b) R = 40 us, S = 10 us
(c) R = 10 us, S = 30 us
(d) R = 30 us, S = 10 us

1. The step size of the DAC of figure is 0.5 V. The value of RF is

(a) 1.6 k
(b) 8 k
(c) 800
(d) 1 k

1. The point P in the following figure is stuck 1. the output f will be

(a) ABC
(b) A
(c) ABC
(d) A

1. It is desired to generate the following three boolean function :

f1 = abc + abc + bc
f2 = abc + ab + abc
f3 = abc + abc + ac
by using on OR gate array as shown in figure where P1 and P5 are the product terms in one or more of the variable a, a, b, b, c and c.
The terms P1, P2, P3, P4 and p5 are
(a) ab, ac, bc, bc, ab
(b) ab, bc, ac, ab, bc
(c) ac, ab, bc, ab, bc
(d) All of these

1. Figure shows a ripple counter using positive edge triggered flip-flops. if the present state of counter is Q2Q1Q0 = 011, then its next state (Q2Q1Q2) will be

(a) 010
(b) 100
(c) 111
(d) 101

1. A 4-bit modulo-6 ripple counter uses j-k fliop-flop. if the propagation delay of each flip-flop is 50 ns, the maximum clock frequency that can be used is equal to

(a) 5 MHz
(b) 10 MHz
(c) 4 MHz
(d) 20 MHz

1. A 12-bit (3-digit) DAC that uses the BCD input code has a full scale output of 9.99 v. the value of VOUT for an input code of 0110 1001 0101 is

(a) 4.11 v
(b) 6.95 v
(c) 7.38 v
(d) 7.88 v

1. Which of the following boolean expression correctly represents the relation between p, Q, R and M1?

(a) M1 = (P OR Q) XOR R
(b) M1 = (P AND Q) XOR R
(c) M1 = (P NOR Q) XOR R
(d) M1 = (P XOR Q) XOR R

1. A logic circuit consist of two 2 x 4 decoder as shown in figure below.

The output of decoder are as follow:
D0 = 1 when A0 = 0,  A1 = 0
D1 = 1 when A0 = 1,  A1 = 0
D2 = 1 when A0 = 0,  A1 = 1
D3 = 1  when A0 = 1,  A1 = 1
The value of f(x,y,z) is
(a) zero
(b) z
(c) z
(d) 1

1. A 4-bit ripple couter and a 4-bit synchronous couter are made by fliap-flops having a propagation delay of 10 us each. if the worst case delay in the ripple couter and the synchronous couter be R and S respectively, then

(a) R = 10 ns, S = 40 us
(b) R = 40 ns, S = 10 ns
(c) R = 10 ns, S = 30 ns
(d) R = 30 ns, S = 10 ns

1. For the circuit shown, the couter state (Q1Q2) follows the sequence

(a) 00, 01, 10, 11, 00…
(b) 00, 01, 10, 00, 01…….
(c) 00, 01, 11, 00, 01………
(d) 00, 10, 11, 00, 10…….

1. The current rating of a TTL series logic gates are IOL(MAX) = 8 mA, IOH(MAX) = – 0.4 mA IIL(MAX) = – 0.1 mA, IIH(MAX) = 20 uA

If all gates are 2-input NAND gate, then fan-out is
(a) 10
(b) 20
(c) 60
(d) 80

1. Refer to the NAND and NOR latches shown in the figure. the inputs (P1, P2) for both the latches are first made (0,1) and then after a few seconds, made (1,1). the corresponding stable outputs (Q1, Q2) are

(a) NAND : first (0,1) then (0,1) NOR: first (1,0) then (0,0)
(b) NAND : first (1, 0) then (1, 0) NOR : first (1, 0) then (1, 0)
(c) NAND : first (1, 0) then (1, 0) NOR : first (0,1) then (0, 0)
(d) NAND : first (1, 0) then (1,1) NOR : first (0,1) then (0,1)

1. The MUX shown in figure is 4 x 1 multiplexer. the output Z is

(a) ABC
(b) A * B * C
(c) A * B * C
(d) A + B + C

1. The present output QN of an edge triggered j-k flip-flop is logic 0. if j = 1, then QN + 1

(a) cannot be determined
(b) will be logic 0
(c) will be logic 1
(d) will race around

1. The circuit shown in figure is

(a) a MOD-2 couter
(b) a MOD-3 couter
(c) generate sequence 00, 10, 01, 00……..
(d) generate sequence 00, 10, 00, 10, 00………..

1. The MOSFET circuit shown in figure implements the function

(a) A (B + C)
(b) ABC
(c) A + BC
(d) A BC

1. A boolean function f of two variables x and y is defined as follows:

f(0,0) = f(0,1) =f(1,1)=1;f(1,0) = 0
Assuming complements of x and y are not available, a minmum cost solution for realizing f using only 2-input NOR gates and 2-input OR gates (each having unit cost) would have total cost of
(a) 1 unit
(b) 4 unit
(c) 3 unit
(d) 2 unit

1. For the circuit of figure consider the statements

Assertion (A) The circuit is sequential.
Reason (R) There is a loop in circuit.
(a) both A and R are true and R is the correct explanation of A
(b) both A and R are true but R is not the correct explanation of A
(c) A is true but R is false
(d) A is false but R is true

1. Consider the RTL gate of figure. the transistor parameters are VCE(SAT) = 0.2 V and B = 50. The logic high voltage is VH = 3.5 V. if input drive the similar type of gate, the fan-out is

(a) 5
(b) 10
(c) 15
(d) 20

1. For the logic circuit shown in figure. the simplified boolean expression for the output Y is

(a) A + B + C
(b) A
(c) B
(d) C

1. The circuit shown in figure has 4 boxes each descrbed by input P,Q,R and output Y,Z with Y = P * Q *R and Z = RQ + PR + QP.

The circuit acts as a 4-bit
(a) adder giving P + Q
(b) Subtractor giving P – Q
(c) subtractor giving Q – P
(d) adder giving P + Q + R

1. The counter shown in figure is a

(a) MOD-8 up counter
(b) MOD-8 down counter
(c) MOD-6 up counter
(d) MOD-6 down counter

1. The circuit of figure acts as

(a) astable multivibrator
(b) monostable multivibrator
(c) bistable multivibrator
(d) none of the above

1. The following binary values were applied to the x and y inputs of NAND latch shown in the figure in the sequence indicated below.

X = 0, = 1, X = 0, Y; X = 1, Y = 1
The corresponsing stable P, Q outputs will be
(a) P = 1, Q = 0; P = 1, Q = 0; P = 1, Q = 0 or P = 0, Q = 1
(b) P = 1, Q = 0; P = 0, Q = 1; P = 0, Q = 1 or P = 0, Q = 1
(c)  P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 0 or P = 0, Q = 1
(d)  P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 1

1. The logic circuit shown in figure implements

(a) D (A . C + AC)
(b) D (B . C + AC)
(c) D (B . C + AB)
(d) D (B . C. + AB)

1. The gates G1 and G2 in figure have propagation delays of 10 ns and 20 ns respectively. if the input VI makes an abrupt change from logic 0 to 1 at time t = t0 then the output waveform VO is
2. The circuit shown in figure implements the function

(a) ABC + ABC
(b) ABC + (A + B + C)
(c) ABC + (A + B + C)
(d) none of these

1. A 4-bit D/A converter is connected to a free- runnung 3-bit up counter, as shown in the following figure. which of the following waveforms will be observed at V0?

In the figure shown above, the ground has been shown by the symbol

1. A sequential circuit using D flip-flop and logic gates is shown in figure, where X and Y are the inputs and Z is the output. the circuit is

(a) s-r flip-flop with inputs x = r and y = s
(b) s-r flip-flop with inputs x = s and y = r
(c) j-k flip-flop with inputs x=j and y=k
(d) j-k flip-flop with inputs x=k and t=j

1. For the circuit shown in the figure D has a transition from 0 to 1 after CLK changes from 1 to 0. assume gate delays to be negligible

Which of the following statements is true ?
(a) Q goes to 1 at the CLK transition and stays at 1
(b) Q goes to 0 at the CLK transition and stays at 0
(c) Q goes to 1 at the CLK transition and goes to 0 when D goes to 1
(d) Q goes to 0 at the CLK transition and goes to 1 when D goes to 1

1. In the circuit in figure S2 to S0 are select lines and X7 and X0 are input lines. S0 and XO are the LSBs. the output is

(a) indeterminate
(b) A . B
(c) A . B
(d) C . (A * B) + C . (A * B)

1. The input signal V1 shown in figure is applied to the flip-flop of figure when initially in 0 state. assume all timing constraints are satisfied. the output Q is
2. The input signal VI shown in figure is applied to a flip-flop of figure when initially in its 0-state. assume all timing constraints are satisfied. the output Q is
3. For each of the positive edge-triggered j-k flip-flop used in the following figure, the propagation delay is T

Which of the following waveforms correctly represents the output at Q1?

1. The circuit diagram of a standard TTL NOT gate is shown in the figure. when VI = 2.5 V, the modes of operation of the transistors will be

(a) Q1 : reverse active Q2 : normal active; Q3 : saturation ; Q4  cut-off
(b) Q1 : Reverse active Q2 : saturation; Q3 : saturation; Q4 : cut-off
(c) Q1 : saturation; Q2 : Saturation; Q3 : cut-off Q4 : saturation
(d) Q1 : saturation: Q2 : Saturation ; Q3 : saturation; Q4 : normal active

1. The full scale output of a 10-bit DAC is 5 V. the resolution is

(a) 5 mV
(b) 10 mV
(c) 2.5 mV
(d) 20 mV

1. For the circuit shown in figure below, two 4-bit prallel-in serial-out shift registers loaded with the data shown are used to feed the data to a full adder. initially, all the flip-flop are in clear state, after applying two clock pulese, the outputs of the full-adder should be

(a) S = 0, C0 = 0
(b) S = 0, C0 = 1
(c) S = 1, C0 = 0
(d) S = 1, C0 = 1

1. The circuit shown in figure implements the functon

(a) (A + B) C + D
(b) (AB + C) D
(c) ( A + B) C + D
(d) (AB + C) D

1. Below circuit of gate in (RTL) resistor transistor logic family. the circuit represents

(a) NAND
(b) AND
(c) NOR
(d) OR

1. The full scale output of a DAC is 10 ma. if resolution is to be less than 40 uA, then required bits are

(a) 11
(b) 10
(c) 8
(d) 9

1. A particular 6-bit DAc has full-scale output rated at 1.260 v. its accuracy is specified as +0.11% of full scale and it has an offset error of +1 mv. the measurement that is not within the DAC specification, is

Input code                                       output
(a) 0 0 0 0 1 0                                               41.5 mV
(b) 0 0 0 1  1 1                                               140.2 mV
(c) 0 0 1 1 0 0                                                   242.5 mV
(d) 1 1 1 1 1 1                                                    1.25 V

1. Match list I and II find the correct answer using the codes given below the lists.

List I                                               List II

1. BCD to 7-segment decoder 1. sequential circuit
2. 4 to 1 MUX 2. combination circuit
3. 4-bit shift register 3. neither sequential nor combinational circuit

Codes
P             Q                R                 S
(a)          2               1                 2                1
(b)          3                 2               1                 3
(c)            2               2                 1                1
(d)            3               1                  2                3

1. minimum number of NAND gate required to implement A (A + B) ( A + B + C) is equal to

(a) 3
(b) 4
(c) 5
(d) none of these

1. For a digital to analog conversion, the bit pattern is 10110

The correct flowing in RF branch is
(a) V/22R
(b) V/66R
(c) V/44R
(d) None of these
Unit Exercise -2

1. (c)
2. (b)

Equation   [X + Z(Y + (Z + XY)][X + Z(X + Y)] = 1
Putting  X = 1 and X = 0
[1 + Z( X + (Z + Y)][0 + Z(1 + Y)] = 1
(1) (Z) = 1
Z = 1
Z = 0

1. (b)

contents 2-4-2-1 BCD number.

1. (b)

as j-k input to all flip-flop made high. the given counter is mode 10.
hence, frequency of output signal
= 10/10 = 1 kHz

1. (c)

Thus, the given CMOS gate satisfies the function of a negative NAND gate.

1. (c)

As MSB is 1 the number in negative. taking 2’s complement of the given number

1. (d)

Writing the expression in canonical form,
AC + BC = AC(B + B) + (A + A) BC
= ABC + ABC + ABC + ABC

1. (d)

F = A + AB + ABC + ABC + ABC (D + DE)
= A + AB + AB(C + C(D + E))
= A + A (B + B(C + D + E) = A + B + C + D + E

1. (a)

this can be wrtten as
= RS(P + Q) + RSP + RSPQ + RSP
= SP + RSP + PQRS + QRS

1. (c)
2. (b)

The largest positive going spike
VNL = VIL(MIN) – VOL(MAX)
= 1 – 0.1 = 0.9 V
The largest negative going spike
VNH = VOH(MIN) – VIH(MIN)
= 4.9 – 3.5 = 1.4 V

1. (b)

in signed 2’s complement the MSB represent the signal
P = 11101101 = (-19)
Q = 11100110 = (-26)10
P-Q = -19 – (-26) = (7)10
(17)10 = 00000111

1. (a)

F1 = AB + AB
F2 = A + B = A.B
X = F1F2
= (AB + AB) . AB
= AB

1. (d)
2. (d)

For LED to glow p = 0
both input to NAND  gate = 1
if any switch is closed AND gate output will be low.
if both switch are open. OR gate output will be low.
hence, LED does not emit light irrespective of switch position.

1. (b)

if input signal E is low, output will not be low. so, it must be high.

1. (c)

C3*C2*C1 = 110 which indicate position 6 in error
transmitted code 1001100.

1. (a)

Truth table
Y = A + AB
X = YC + YC = (AB + AB) C + (AB + AB)C
= ABC + ABC + ABC + ABC

1. (a)

This is a 5-bit synchronous counter. when the output of Q3 and Q4 is high then, the output of NAND gate is low. this will clear all flip-flops. so, it is a mod-24 counter.
When 11000 occur the CLR input is activated and all flip-flops are immediately cleared.

1. (c)

The timing diagram of modulo-6 ripple counter
i.e., in modulo-6 counter at 110 all state must be cleaned CB = 1.
C = B = 0 and output of 20 input gate is also 0.
hence, OR gate required 40 perform the decimal function.

1. (a)
2. (d)

in 2’s complement
A = 01000110
B = 11010011
A,B represents the 2’s complement of A and B respectively

1. (d)
2. (c)

The minimum number of 2 to 1 multiplexer required to realize 4 to 1 MUX is 3.

1. (b)

VNH = VOH(MIN) – VIH(MIN)
VIH(MIN) = VOH(MIN) – VNH
= – 0.8 – 0.5 = – 1.3 V
VNL = VIL(MAX) – VOL(MAX)
VIL(MAX) = VNL+ VOL(MAX)
= 0.5 + (-2)
= – 1.5 V

1. (C)
2. (d)
3. (c)

After t = t1 – shift regist output e = 0110(6)
input of address line of ROM at 6; 1010 is stored.
At next rising edge of clock 1010 (10) the stored data in ROM 1000

1. (a)

F1 = A + B
= A . B = A . B
Z = AB . B.C
= ABC

1. (a)
2. (c)
3. (a)

for 2 input AND gate,
Y = AB
Y = AB + AB

1. (b)

fall-out minimum – DTL (undesired)
power consumption is minimum – CMOS (Desired)
propagation delay is minimum – ECL – (Desried)

1. (a)

F1 = AB
F2 = (B + C)
Z = F1.F2
= (AB).(B + C)
= ABC

1. (c)
2. (a)

from truth table we can invite
f = ABC + ABC = B(AC + AC)
= B (A + C) (A + C)

1. (d)

F = I0S1S0 + I1S1S0 + I2S1S0 + I3S1S0
I0 = C
I1 = D
I2 = C
I3 = C .D
S1 = A
S0 = B
F (A, B, C, D) = ABC + ABD + ABC + ABC D
= ABC (D + D) + AB (C + C) D + ABC (D + D) + ABC D
= ABCD + ABC D + ABCD + ABCD + ABCD + ABC D + ABC D
= M (2, 3, 5, 7, 8, 9, 12)

1. (a)

The truth table
D0 = Q1
D1  = Q0
Hence, the inputs D0 and D1 should be connected to Q1 and Q0 respectively.

1. (b)

the simpiified diagram
we can write
VA = 1/8 + 1/2 = 5/8
VA = V8 = 5/8 V
KVL at node B,
0 – 5/8 5/8 – V0
8/1K = 8/7K
V0 = 5 V

1. (a)

Y = RS + PR + PQ + PQ
= RS + (PR . PQ . PQ)
= RS + (P + R) (P + Q) (P + Q)
= RS + (P + PR + PQ + RQ) (P + Q)
= RS + (PRQ + PQ + PQR + PQ + QR)  [PP = 0]
= RS + PQ + QR (P + P + 1)
= RS + PQ + QR
= R + S + PQ + PQR + PQS
By simplifing
Z = R + S + PQ + PR + PQS + QRS
= R (1 + P + QS)+ S (1 + PQ) + PQ
= R + S + PQ
We can write
W = Z and X = Z

1. (a)

F = BD + BCD + ABD

1. (d)

As shown in figure.
the select line for chip # 1 is A8 + A9.
The select line for chip # 2 is A8 + A9. Hence, the memory address range F800 – F9FF is not represented by chip # 1 and chip #2.

1. (a)

we can write
V0 = – V1 (R/R B0 + R/2R B1 + R/4R B2 + R/8R B3)
For V1 = 5 V,
V0 = – 5 (1 + 1/2 + 1/4 + 1/8)
= – 9.375 V
With maximum tolerance 10% in voltage and 5% inresistors
VO = – 5.5 (110/90 x 110/2×90 + 110/4×90 + 110/8×90
= – 12.604
tolerance = 12.604 – 9.375/9.375 x 100 = 34.44%

1. (d)

Y = ABCD + ABCD + ABCD + ABC D
= ABCD + ABC D + BCD (A + A)
= ABCD + ABC D + BCD

1. (d)

f = AC + BC
= AC (B + B) + BC (A + A)                (B + B) = 1
= ABC + ABC + ABC + ABC

1. (c)

after t = t1 at the first rising edge of clock, the output of shift register is 0110, which is input to address line of ROM, at 0110 (6) data 1010 is stored which will be on bus. at next rising edge of clock 1010 is applied to register. so, at this time data stored in ROM at 1010 (10), 1000 will be on bus.

1. (c)

As circuit has one stable state and require external triggering to change state. so, it represnts a multistable multivibrator.

1. (c)

Boolean expression
= (X + Y)(X + Y) (X + Y)
= (X + XY + XY) (X + Y)
= XY + XY
= XY

1. (a)

let the output from the upper first level multiplexer and from the lower first level multiplexer is f2.
f1 = wx + wx
f2 = wx + wx = x(w + w) = x
f = f1yz + f2yz + yz
= (wx + wx) yz + xyz + yz
f = wxyz + wx yz + xy + yz

1. (c)

here, 101 repeat itselt after every two cycles. the output Q2Q1Q0 will be
= fc/2

1. (a)

hence, e(Q1Q2) sequence
11, 10, 00, 11, 10

1. (c)

width of one pulse = 1/10 x 106
= 0.1 us
width for 1 V = 10 us
for 10 V = 10 x 10
so, corresponding pulse count = 100/0.1 = 1000

1. (d)

Z = A + (AB + BC) + C
= A + (A + B + B + C) + C
= A + B + C
and AB + BC + CA = A + B + B + C + C + A = A + B + C

1. (b)

I0 = 0
I1 = y + z
I3 = yz + yz = y . z
I2 = z

1. (c)
2. (b)

in ripple counter clock will propagate through each flip-flop. hence worst case delay in ripple counter = 4 x 10 ms = 40 ms.
in synchronous counter clock will be given simultaneously to all flip-flops. hence, worst case delay will be = 10 ms.

1. (c)

for the circuit
step size = RF/8K x 5
0.5 = RF/8K x 5
RF = 800

1. (d)

when P stuck at 1. the x will be 1 whatever be other input B and C. hence, the output f as shown above is A.

1. (a)

F1 = abc + abc + bc = ac + ab
F2 = abc + ab + abc = ac + be
F3 = abc + abc + ac = ab + bc
thus, P1 = ab, p2 = ac, p3  = bc, p4 = bc, p5 = ab

1. (b)

the given ripple counter is positive edge triggered flip-flop. hence, at every clock Q2 Q1 Q0  will be changed. the present state is 011, the next state will be 100.

1. (a)

for a 4-bit modulo-6 counter
number of flip-flops = 4
total delay = 4 x 50 us = 200 x 10-9
so, maximum frequency = 1/200 x 10-9
= 5 MHz

1. (b)

step size = 9.99/999 = 10 mV
input code = 0110 1001 01012
= 69510
so, output voltage VOUT will be
VOUT = 695 x 10
= 6950 mV
= 69.5 V

1. (d)
2. (d)

DO = A1A0, D1 = A1A0, D2 = A1A0
For output f
for first decoder A0 = x, A1 = Y, D2 = YX, D3 = XY
For second decoder A1 = D2D3 = YXXY = 0, A0 = Z
F = D0 + D1 + A1A0  + A1A0 = A1 = 1

1. (b)

for a 4-bit ripple counter
R = Delay = 4 x 10
= 40 us
for a synchronous 4-bit counter
S = Delay = 10 ns
Q1Q2 = 00, 01, 10, 00, 01……..

1. (b)

fan-out (low) = IOL(MAX)/IIL(MAX) = 8/0.1 = 80
Fan-out (high) = IOH(MAX)/IIH(MAX) = 400/20 = 20
The fan-out is chosen the smaller of the two. so, the fan-out will be 20.

1. (c)

fan NAND gate in any one input is zero, then its output will be 1. so if p1 is zero the Q1 becomes 1. now we can calculate Q2 because its both inputs are 1, so Q2 will be zero. by using these values of Q1 and Q2 as feedback with new input new value of Q1  and Q2 can be calculated.

1. (a)

output Z,
Z = S0S1. 1 + S0S1.1 + S0S1.1 + S0S1C
Put S0 = A and S1 = B,
Z = AB + AB + AB + ABC
= ABC + ABC + AB + AB + ABC

1. (c)

the j-k truth table,
hence, QN+1 will be 1.

1. (b)

after three clock pulses the flip-flops are cleared. thus the circuit represents the MOD-3 counter.

1. (c)

if A = – VDD then M1 is on and Y = 0 V
If B = C = – VDD and A = 0, then M3 and M2 are on but M1 is off hence Y = 0 V.
If B = C = 0 then M1 is off and either or both M2 and M3 will be off, which implies on current flowing through M4 hence, Y = – VDD
Thus, given circuit satisfies the logic equation A + BC.

1. (d)

the truth table
we can write
f = xY + xy + xy
= x (y + y) + xy
= x + xy
= x + y
the circuit realization
hence, one NOR and one OR gate are required As each having one unit cost. hence, the minimum cost required is  2 unit.

1. (d)

here in the circuit no active loop in the network because variable b interrupts the loop t two different points.
when b = 1
Z1 = Z0d, Z0 = e + c
when b = 0,
thus, there is no feedback of signals in the physical loop and the circuit is combinational.

1. (c)

for each successive gate, that has a transistor in saturation, the current required is
IB(SAT) + IC(SAT)/B = VCC – VCE(SAT)/BRC = 5 – 0.2/50(640)
= 0.15 mA
For n attached gate I0 = nIB(SAT)
to assure no logic error V0 = VCC – IORC > VH = 3.5 V
n < VCC – 3.5/RCIB(SAT) = 5 – 3.5 /640 (0.15) = 15.6
n < 15

1. (c)
2. (b)

this is a 1-bit subtract or with R as borrow.
Y = P * Q * R
Z = RQ + PR + QP
Hence, perform P-Q operation.

1. (b)

let initial state is 000,
because 0 state of previous flip-flops changes the state of next so it is a down counter.

1. (a)

lnitially let us consider at  t = 0, the voltage across capacitor VC = V(0) and V0 = V(1), the output VO will charge capacitor C with the time constant t = RC. when VC reaches to V(1) the output of inverter goes to V(0) and the capacitor starts discharging thus, the square waveform will be generated at the output.

1. (c)
2. (d)

Z = D (ABC + ABC + ABC + ABC + ABC)
= D(AB(C + C) + BC (A + A) + ABC)
= D(AB + BC + ABC) = D(B(A + AC) + BC)
= D (BA + BC + BC) = D (B . C + AB)

1. (b)

the timing diagram

1. (b)

if all inputs A, B, C are high, then
input to inverter low
output Y = High
if all the inputs A, B, and C are low, then
input to inverter = low
output Y = high
thus Y = ABC + ABC = ABC + (A + B + C)

1. (b)
2. (d)

the truth table for given D flip-flop
Z = XQ + YQ
The equation of J-K flip-flop
QN+1 = JQN + KQ
X = K and Y = J

1. (a)
2. (a)
3. (c)

the flip-flop shown in the circuit is a negative edge triggered T flip-flop. so, at the negative edge of the clock VI flip-flop will invert the output, if there is 1 at input.

1. (a)
2. (b) given clock pulse
3. (a)
4. (a)

resolution  = VFS/2N – 1
= 5/210 – 1 = 5/1024 – 1 = 5/1023 = 5 mV

1. (d)

after applying 1 st CLK PUBE,
A – 1
B – 0
C – 0
S – 0
CO – 1
After applying 2nd CLK PUBE,
A – 1
B – 1
C – 1
S – 1
C0 – 1

1. (c)

the operation of circuit is given below.
from the table, output can be summarized as
Y = (A + B) C + D

1. (d)

(i) V1 = 0 and V2 = 0  Q1  = Q2 = off
VB = VCE. = VCE2 = VCC
Q3 = On, V0 = 0
(ii) V1 = 0 and V2 = 1
Q1 = off, Q2 = On, VB = Q3 = off
or V0 = 1
(iii) V1 = 1 and V2 = 0
Q1 = On , Q2 = Off VB = VCE2
Q3 = Off V0 = 1
(iv) V1 = 1 and V2 = 1
Q1 = Q2 = on, VB = 0
Q3 = Off
VO = VCE3 Or V0 = 1
V0 = V1 + V2

1. (c)

resolution = 40 uA
the step required = 10 m/40 u = 250
therefore, it required 8-bit.

1. (b)

step size = 9.99/999 = 10 mV
0110   1001     0101
6             9           5
695 x 10 m = 6.95 v
(c) step size = 1.26/63 = 20 mV
+ 0.1%F.3 = + 1.26 V
Maximum total error = + 1.26 + 1 = 2.26 mV
0000102 = 2 x 20 m = 40 mV
(41.5 mV is within specs.)
0001112 = 7 x 20 m = 140 mV
(140.2 mV is within specs.)
0011002 = 12 x 20 m = 240 mV
(242.5 mV isn’t within specs.)
111112 = 63 x 20 m = 1.26 v
(1.258 is within specs.)

1. (c)
2. (d)

F = A (A + B) (A + B + C)
= (A + AB) (A + B + C)
= A + AB + AC + AB + AB + ABC
= A (1 + B + C + B + B + BC)
= A
So, there is no need of NAND gate

1. (a)