simplify f (a, b, c, d)=σm(0, 2, 4, 6, 7, 8, 9, 11, 12, 14) | the minimized expression for boolean function using k map

the minimized expression for boolean function using k map simplify f (a, b, c, d)=σm(0, 2, 4, 6, 7, 8, 9, 11, 12, 14) ?
Unit Exercise – 1
(1 mark Questions)

the Boolean expression (XYZ + YZ + XZ) after simplification

(a) X
(b) Y
(c) Z
(d) (X + Y) Z

Match the logic gate in column A with their equivalents in column B and find the correct answer using the codes given below the columns.
if (211)_x = (152)₈, then the value of base x is

(a) 6
(b) 5
(c) 7
(d) 9

the logic circuit given below converts a binary code Y₁ Y₂ Y₃ into

(a) excess-3 code
(b) gray code
(c) BCD code
(d) hamming code

the number of product terms in the minimized sum-of-product expression obtained through the following k-map is (where d denotes don’t care states)

(a) 2
(b) 3
(c) 4
(d) 5

the minimized expression for Boolean function f(w, x, y, z) = IIm (0, 1, 4, 5, 8, 9, 11) + DC (2, 10) is

(a) (w + x) (w + y)
(b) (w + y) (w + x)
(c) (w + y) (w + x)
(d) (w + x) (w + y)

An OR gate has 6 inputs. how many input words are there in its truth table?

(a) 6
(b) 36
(c) 64
(d) 64000

the boolean function y = AB + CD is to be realized using only 2-input NAND gates. the minimum number of gates required is

(a) 2
(b) 3
(c) 4
(d) 5

the MUX shown in figure is a 4 x 1 multiplexer. the output Z is

(a) A * C
(b) A . C
(c) B * C
(d) B . C

Match logic family list I with their properties given in list II and select the correct answer using the codes given below the lists.
the voltage level for negative logic system

(a) must necessarily be negative
(b) must necessarily be positive
(c) need not be negative
(d) must be necessarily 0 v and – 5 v

identify the operation of circuit in negative level logic system.

(a) AND
(b) OR
(c) NAND
(d) NOR

Which of the following identities is true?

(a) A + BC = (A + B) (A + C)
(b) A + BC = (A + B) (A + C)
(c) A + BC = (A + B) (A + B)
(d) A + BC = (A + B) (A + C)

Match list I with list II and find the correct answer using the codes given below the lists.
the resolution of a 8-bit A/D converter is

(a) 0.01%
(b) 0.024%
(c) 0.024%
(d) 0.40%

X = 01110 and Y = 11001 are two 5-bit binary numbers represented in 2’s complement format. the sum of X and Y represented in 2’s complement format using 6-bit is

(a) 100111
(b) 001000
(c) 000111
(d) 101001

4-bit 2’s complement representation of a decimal number of 1000. the number is

(a) + 8
(b) 0
(c) – 7
(d) – 8

the number of comparators required in a 3-bit comparato type ADC is

(a) 2
(b) 3
(c) 7
(d) 8

the range of signed decimal numbers that can be represented by 6-bit 1’s complement number is

(a) – 31 to + 31
(b) – 63 to 64
(c) – 64 to 63
(d) – 32 to + 31

for the logic circuit below, the output Y is equal to

(a) ABC
(b) A + B + C
(c) AB + BC + A + C
(d) AB + BC

Implement Y = A + BC + AC requires minimum number of NAND gates are

(a) 4
(b) 6
(c) 5
(d) 3

consider the boolean expression : X = ABCD + ABCD + ABCD + ACBD

The simplified form of X is
(a) C + D
(b) BC
(c) CD
(d) BC

The minimum boolean for the following circuit is

(a) AB + AC + BC
(b) AB + BC
(c) ABC + AC
(d) ABC

The 2’s complement representation of – 17 is

(a) 01110
(b) 01111
(c) 11110
(d) 10001

the circuit given below is

(a) J-K flip-flop
(b) johnson’s counter
(c) RS latch
(d) none of these

there are four boolean variables x₁, x₂, x₃ and x₄ the following function are defined on sets of them

f(x₃, x₂, x₁) = m(3, 4, 5)
g(x₄, x₃, x₂) = m(1, 6, 7)
h(x₄, x₃, x₂, x₁) = fg
then h(x₄, x₃, x₂, x₁) is
(a) m (3, 12, 13)
(b) m (3, 6)
(c) m (3, 12)
(d) 0

the value of X . 1 is

(a) X’
(b) X
(c) 1
(d) 0

Given that for a logic family

V_OH is minimum output high level voltage.
V_OL is maximum output low level voltage
V_IH is minimum acceptable input high level voltage
V_IL is maximum acceptable input low level voltage
the correct relationship is
(a) V_IH > V_OH > V_IL > V_OL
(b) V_OH > V_IH > V_IL > V_OL
(c) V_IH > V_OH > V_OL > V_IL
(d) V_OH > V_IH > V_OL > V_IL

Without any additional circuitry, a 8 : 1 MUX can be used to obtain

(a) some but not all boolean functions of 3 variables
(b) all function of 3 variables but none of 4 variables
(c) all functions of 3 variables and some but not all of 4 variables
(d) all function of 4 variables

A 0 to 6 counter consists of 3 flip-flops and a combination circuit of 2 input gate(s). the combination circuit consists of

(a) one AND gate
(b) one OR gate
(c) one AND gate with one OR gate
(d) two AND gates

The boolean function f implemented in figure using two input multiplexers

(a) ABC + ABC
(b) ABC + ABC
(c) ABC + ABC
(d) ABC + ABC

For MOD – 12 counter, the flip-flop has a t_po = 60 ns. the NAND gate has a t_pd of 25 ns. the maximum clock frequency is given by

(a) 37.74 MHz
(b) 377.4 MHz
(c) 3.774 MHz
(d) None of these

A master slave flip-flop has the charactteristic that

(a) change in the input immediately reflected in the output
(b) change in the output occurs when the state of the master is affected
(c) change in the output occurs when the state of the slave in affected
(d) both the master and the slave states are affected at the same time

The combinational logic circuit shown in given figure has an output Q which is

(a) ABC
(b) A + B + C
(c) A . B. C
(d) A * B * C

Express 8⁴ in octal system is

(a) (1000)₈
(b) (10000)₈
(c) (10100)₈
(d) (10100)₈

An 8-bit successive approximation A/D convertor has full scale reading of 2.55 v and its conversion time for an analog input of 1 v is 20 us. the conversion time for a 2 v input will be

(a) 10 us
(b) 20 us
(c) 40 us
(d) 50 us

Among the given array for making 16384 bit memory, which combination is usually preferred

(a) 64 row x 256 column
(b) 256 row x 64 column
(c) 128 row x 128 column
(d) 512 row x 32 column

if the minimum output voltage of a 7-bit D/A is 25.4 v. what is the smallest change in the output as the binary count increase?

(a) 0.2 v
(b) 0.5 v
(c) 25.9 v
(d) 0.1 v

A digital system is required to amplify a binary encoded audio signal. the user should be able to control the gain of the amplifier from a minimum to a maximum in 100 increments. the minimum of bit required to encode in straight binary is

(a) 8
(b) 6
(c) 5
(d) 7

the logic family which is most suitable in the indusrial environment is

(a) I²L
(b) HTL
(c) TTL
(d) CMOS

Wired logic is not possible in

(a) ECL
(b) TTL with active pull-up
(c) open-collector TTL
(d) TTL with passive pull-up

the switching speed of ECL i very high because

(a) it uses positive logic
(b) it uses negative logic
(c) it uses high speed transistors
(d) its transistors remain unsaturated

identiy and logic gate family which consume maximum power and which has minimum propagation delay

(a) MOS
(b) TTL
(c) ECL
(d) CMOS

for the output F to be 1 in the logic circuit shown, the input combination should be

(a) A = 1, B = 1, C = 0
(b) A = 1, B = 0, C = 0
(c) A = 0, B = 1, C = 0
(d) A = 0, B = 0, C = 1

The full form of the abbreviations TTL and CMOS in reference to logic families are

(a) triple transistor logic and chip metal oxide semiconductor
(b) tristate transistor logic and chip metal oxide semiconductor
(c) transistor logic and complementary metal oxide semiconductor
(d) tristate transistor logic and complementary metal oxide silicon

Decimal 43 in hexadecimal and BCD number system is respectively

(a) B2, 0100 0011
(b) 2B, 0100 0011
(c) 2B, 0011 0100
(d) B2, 0100 0100

The number of distinct boolean expression of 4 variables is

(a) 16
(b) 256
(c) 1024
(d) 65536

The minimum number of comparators required to build an 8-bit flash ADC is

(a) 8
(b) 63
(c) 255
(d) 256

the output of the 74 series of TTL gates is taken from a BJT in

(a) totem pole and common collector configuration
(b) either totem pole or open collector configuration
(c) common base configuration
(d) common collector configuration

if the input to the digital circuit (figure) consisting of a cascade of 20 XOR – gates is X, then the output Y is equal to

(a) 0
(b) 1
(c) X
(d) X

A 3stage walkingar creeping is given below.

how many states does this counter pass through before repeating? what is the modulo?
(a) 3
(b) 8
(c) 2
(d) the modulo cannot be determined given this information

the simplified form of a logic function Y = A (B + C(AB + AC)) is

(a) AB
(b) AB
(c) AB
(d) AB

Initially Q_O = Q₁ = 0. What will be the logic states of Q_O and Q₁ immediately after 777th clock pulse for the figure shown below.

(a) 01
(b) 10
(c) 11
(d) 00

in the logic circuit of figure the redundant gate is

(a) 1
(b) 2
(c) 3
(d) 4

the gate shown in figure is

(a) AND gate
(b) NAND
(c) NOT
(d) OR gate

The divide by N counter is shown in figure. if initially Q_O= 1, Q₁ = 1, Q₂ = 0. What is a value of N?

(a) 8
(b) 6
(c) 5
(d) 3

identify the logic gate family, which is slowest among the given logic?

(a) ECL
(b) TTL
(c) CMOS
(d) I²L

The power consumption is more for which of the following logic gate family?

(a) ECL
(b) TTL
(c) CMOS
(d) DCTL

A switching function

f(A, B, C, D) = A’ B’ CD + A’ BC’D + A’BCD + AB’C’D + AB’CD
Can also be written as
(a) m (1, 3, 5, 7, 9)
(b) m (3, 5, 7, 9, 11)
(c) m (3, 5, 9, 11, 13)
(d) m (5, 7, 9, 11, 13)

the switching function f(A, B, C, D) = M(5, 9, 11, 14) Can be written as

(a) A’ BC’ D + AB’ C’ D+ AB’ CD + ABCD’
(b) A’ B’ C’ D + AB’ C’ D + A’ B’ CD + ABCD’
(c) A’ BC’ D + A’ BC’ D’ + AB’ CD’ + ABCD
(d) none of the above

the switchin function

f(A, B, C) = (A + B’ + C) (A’ + B’ + C) (A + B’ + C’)
can also be written as
(a) m (2, 3, 6)
(b) m (0, 1, 4, 5, 7)
(c) m (1, 2, 5, 6, 7)
(d) m (0, 2, 4, 6)

the othercanonical form of f (A, B, C) = M (0, 1, 5, 7) is

(a) IIM (2, 3, 4, 6)
(b) IIM (2, 4, 6, 8)
(c) IIM (2, 5, 6, 7)
(d) IIM (1, 3, 5, 7)

If a three variable switching function is expressed the product of maxterms by

f (A, B, C) = IIM (0, 3, 5, 6)
Then it can be expressed as the sum of minterms by
(a) m (0, 3, 5, 6)
(b) IIM (1, 2, 4, 7)
(c) m (1, 2, 4, 7)
(d) IIM (1, 2, 4, 7)

The dual of boolean theorem x (y + z) = xy + xz is

(a) x + yz = xy + xz
(b) x (y + z) = (x + y) (x + z)
(c) x + yz = (x + y) (x + z)
(d) none of the above

what is frequency of the pulse at point a, b, c, d in circuit?

(a) 20 Hz, 500 Hz, 33.25 Hz, 3.9 Hz
(b) 10 KHz, 500Hz, 31.25 Hz, 3.9 Hz
(c) 10 Hz, 500 KHz, 31.25 KHz, 3.8 Hz
(d) 100 KHz, 50 KHz, 31.25 MHz, 3.6 Hz

The J-K flip-flop shown in figure is initially cleared and then clocked for 5 pulses, the sequence at the Q output will be

(a) 0 1 0 0 0 0
(b) 0 1 1 0 0 1
(c) 0 1 0 0 1 0
(d) 0 1 0 1 0 1

output Y is equal to

(a) (A + B) C + DE
(b) AB = C (D + E)
(c) (A + B) C + D + E
(d) (AB + C) DE

An AB flip-flop is constructed from an SR flip-flop as shown in figure. the expression for next state Q⁺is

(a) AB + AQ
(b) AB + BQ
(c) both A and B
(d) None of these

output Y is equal to

(a) AB CD EF
(b) AB + CD + EF
(c) AB + CD + EF
(d) (A + B) (C + D) (E + F)

The diode logic circuit of figure is a

(a) AND
(b) OR
(c) NAND
(d) NOR

Choose the correct statement from the following.

(a) PROM contains a programmable AND array and a fixed OR array
(b) PLA contains a fixed AND array and a programmable OR array
(c) PROM contains a fixed AND array and programmable OR array
(d) None of the above

2’s coplement representation of a 16-bit number (one sign bit and 15 magnitude bit) is FFFI. its magnitude in decimal representation is

(a) 0
(b) 1
(c) 32.767
(d) 65.767

the maximum positive and negative numbers which can be represented in 2’s complement form using n-bit are respectively,

(a) + (2^n-1 – 1), – (2^n-1 – 1)
(b) + (2^n-1 – 1), – 2^n-1
(c) + 2^n-1, – 2^n-1
(d) + 2^n-1, – (2^n-1 + 1)

the maximum positive and negative numbers that can be represented in ones complement using n-bit are respectively,

(a) + (2^n-1 – 1) and – (2^n-1 – 1)
(b) + (2^n-1 – 1) and – 2^n-1
(c) + 2^n-1 and – (2^n-1 – 1)
(d) none of the above

the CMOS circuit shown in figure is a

(a) positive NOR
(b) negative NOR
(c) Positive NAND
(d) negative NAND

The circuit shown in figure acts as a

(a) NAND
(b) NOR
(c) AND
(d) OR

The circuit shown in figure is

(a) NAND
(b) NOR
(c) AND
(d) OR

the minimized expression for boolean function f(w, x, y, z) = m (0,1,4,5,8,9,11) + dc (2, 10) is

(a) (w + x) (w + y)
(b) (w + y) (w + x)
(c) (w + y) (w + x)
(d) (w + x) (w + y)

A combinational circuit has input A, B and C and its k-map is as shown ahead. the output of the circuit is given by

(a) (AB + AB) C
(b) (AB + AB) C
(c) ABC
(d) A * B * C

The minimum function that can detect a divisible-3 8421 BCD code digit (representation D₈D₄D₂D₁) as given by

(a) D₈D₁ + D₄D₂ + D₈D₂D₁
(b) D₈D₁ + D₄D₂D₁ + D₄D₂D₁ + D₈D₄D₂D₁
(c) D₄D₁ + D₄D₂ + D₈D₁D₂D₁
(d) D₄D₂D₁ + D₄D₂D₁ + D₈D₄D₂D₁

Find f(x₂, x₁, x₀) = ?

(a) (1,2,4,5,7)
(b) (1,2,4,5,7)
(c) (0,3,6)
(d) none of these

t₁t₂ = ?

(a) x₀x₁x₂
(b) x₀ * x₁ * x₂
(c) 1
(d) 0

given two number A and B in sign magnitude representation in an 8-bit format A = 00011110 and B = 10011100, the corresponding decimal numbers respectively are

(a) 30 and 156
(b) 14 and -12
(c) 30 and -100
(d) -28 and 30

(177)₈ + 1 = (x)_8,the value of x is

(a) 178
(b) 179
(c) 200
(d)none of these

the building block shown below is a active high output decoder.

the output X is
(a) AB + BC + CA
(b) A + B + C
(c) ABC
(d) none of these

the network shown below implements

(a) NOR gate
(b) NAND gate
(c) XOR gate
(d) XNOR gate

the output of the 4 x 1 multiplexer shown below is

(a) x + y
(b) x + y
(c) xy + x
(d) xy

for the logic circuit shown below, the input y is

(a) A * B
(b) A * B
(c) A * B * C
(d) A * B * C
90.The 8-to-1 multiplexer shown ahead is realize the following boolean expression
(a) wxz + w x z + wyz + xyz
(b) wxz + w yz + wyz + w xy
(c) w x y + w x z + wxz + y zw
(d) MUX is not enable

the initial contents of 4-bit serial in-parallel out right shift, register shown beow is 0110. after three clock pulses are applied, the contents of shift register will be

(a) 0000
(b) 0101
(c) 1010
(d) 1111

a 10-bit D/A converter provides an analog output which has a maximum value of 10.23 v. the resolution is

(a) 10 mV
(b) 20 mV
(c) 15 mV
(d) 25 mV

A memory system of size 16 kB is required to be designed using memory chips which have 12 address lines and 4 data lines each. number of such chips required to design the memory system will be

(a) 2
(b) 4
(c) 8
(d) 16

A 8-bit successive approximation ADC has full scale reading of 2.55 V and conversion time for an analog inpt of 1 V is 20 us. conversion time for a 2V input is

(a) 10 us
(b) 20 us
(c) 40 us
(d) 50 us

A 10-bit A/D converter is used to digitize an analog signal in 0-5 v range. the maximum peak to peak ripple voltage that can be allowed in DC voltage is

(a) nearly 100 mV
(b) nearly 50 mV
(c) nearly 25 mV
(d) nearly 5 mV

A particular logic family exhibits the following characteristics :

V_NL (low noise margin = 0.5 v
V_NH (high noise margin) = 0.5 v
V_OH(MIN) = – 0.8 V
V_OL(MAX) = – 2 V
the V_IH(MIN) and V_IL(MAX) Will be
(a) -1.3 v, 2.5 v
(b) -0.3 v, 2.5 v
(c) -1.3 v, -1.5 v
(d) -0.3 v, -1.5 v

For a DAC the resolution required is 50 mv and the total maximum input is 10 v. the number of bit required is

(a) 7
(b) 8
(c) 9
(d) 200

A read/write memory chip has a capacity of 64 kB. assuming separate data and address lines and availability of chip enable signal, the minimum number of pins required in the IC chip is

(a) 28
(b) 26
(c) 24
(d) 22

In a dual slope integrating ADC, the first integration is carried out for 10 periods of the supply frequency of 50 Hz. if the reference voltage used is 2 v, the total conversion time for an input 1 v is

(a) 1 s
(b) 0.5 s
(c) 0.4 s
(d) 0.1 s

How many address lines are needed to address each memory location in 2084×4 memory chips?

(a) 10
(b) 11
(c) 8
(d) 12
Answers with Solutions
Unit Exercise – 1

Boolean expression
F = XYZ + YZ + XZ
= YZ (1 + X) + XZ
= YZ + XZ [ 1 + X = 1]
= (X + Y) Z

The equivalent pair

(211)_x = (152)₈
2x² + x + 1 = 1 x 8² + 5 x 8 + 2 x 8⁰
2x² + x + 1 = 64 + 40 + 2
2x² + x + 1 = 106
2x² + x – 105 = 0
After solving the equation, we get
x = 7

Truth table of the given function.
From the truth table, we see that the outputs are in the form of gray code. as

Taking don’t care condition as 0
Y = BD + ACD
Number of product term = 2

f(w,x,y,z) = IIm (0,1,4,5,8,9,11) + dc (2,10)
Forming the k-map
f(w,x,y,z) = (w + y) (w + x)

Number of inputs = 6
Number of words = 2⁶ = 64

Y = AB + CD = AB + CD = AB . CD
The minimum number of 2-input NAND gates = 3

Z = ABC + ABC + ABC + ABC
= AC (B + B) + AC (B + B)
= AC + AC [ (B + B) = 1]
= A * C

TTL = High switching speed and good fan-out capability.
ECL = Non-saturation type and high power consumption.
CMOS = Low power consumotion and high packing density.
I²L = Bipolar logic with high packing density.

For negative logic system one of the voltage level must be negative.

The truth table for the given function
Y = A + B = NOR

Checking all the alternatives
(a) A + AC + AB + BC = A + BC
i.e., false
(b) AC + AB + BC
i.e., false
(c) AC + AB + BC = AC + AB = BC + AA = A (A + B) + C (A + B) = (A + C) (A + B)
Which is = LHS, i.e., false
(d) A + AC + AB + BC = A (1 + C) + AB + BC = A + BC = i.e., LHS is true

Shift register – for parallel to serial conversion
Multiplex – As a many to one switch
Decoder – To generate memory chip select

Percentage resolution = 1/2ⁿ – 1 x 100
= 1/2⁸ – 1 x 100
= 0.39%
= 0.40%

X + Y = 0 0 1 1 1
In 6-bit form
X + Y = 0 0 0 1 1 1

since, the MSB is 1 so, the decimal representation will be
= – (2’s complement of 1 0 0 0)
= – (1 0 0 0)
= – 8

The number of comparator required for n-bit comparator type ADC is 2ⁿ – 1
For n = 3; number of comparator required 2³ – 1 = 7.

For 1’s complement, the range of signed decimal number is
– (2^n-1 – 1) to + (2^n-1 – 1)
For n = 6, range wil be 31 to + 31.

f₁ = A . B
f₂ = B. C
f₃ = A . B + B.C
= A + B + B + C
= A + B + C
Y = A + A + B + C + C
= A + B + C

simplify the function with the help of de-morgons theorem,
here, Y = A + BC + AC = A + BC + AC
= A . BC . AC
Implementing the function with NAND gates
Thus, 5 NAND gates are required for implementing the function.

X = ABCD + ABCD + ABCD + ACD
= BCD (A + A) + ABCD + ACBD
= BCD + BCD (A + A)
= CD (B + B)
= CD

Ripple counter – 2ⁿ
Johnson counter – 2N
Ring counter – N
Sequence counter – 2ⁿ – 1

f₁ = A (B + C)
F₂ = AB
F₃ = (A + B)C
and Y = F₁ + F₂ + F₃
= A (B + C) AB + (A + B) C
= AB + AC + AB + AC + BC
= AB + BC + CA

(17)₁₀ = (010001)₂
2’s complement of + 17 will be equivalent to -17 so,
– 17 = 101111

This circuit represents RS latch

f(x₃, x₂, x₁) = m(3, 4, 5)
f = x₃x₂x₁ + x₃x₂x₁ + x₃x₂x₁
= x₃x₂x₁ + x₃x₂ + (x₁ + x₁)
= x₃x₂x₁ + x₃x₂
g(x₄, x₃, x₂) = m (1, 6, 7)
g = x₄x₃x₂ + x₄x₃x₂ + x₄x₃x₂
= x₄x₃x₂ + x₄x₃
h = f . g = (x₃x₂x₁ + x₃x₂). (x₄x₃x₂ + x₄x₃)
= x₄x₃x₂x₁ + x₄x₃x₂x₁ + x₄x₃x₂x₁
h = m(3, 12, 13)

X . 1 = X . 1 + X . 1
= X + X . 0
= X

Thus, the relationship between the input levels will be
V_OH > V_IH > V_IL > V_OL

All function of 4 variable can be inplemented using 8 : 1 MUX.

0-6 counter
Therefore, two NAND gates are required.

E = BC + BC
F = E . O + E . A
= (BC + BC) A
= ABC + ABC

maximum frequency is given by
f_max < 1/t_s + ntpd
where, n = number of flip-flop
t_s = propagation delay of gate
t_pd = propagation delay of flip-flop
For implementing mod-12 counter we require 4 flip-flop so
f_max < 1/(25 x 10^-9 + 4 x 60 x 10^-9)
f_max < 3.774 MHz
Therefore, maximum frequency is 3.774 MHz.

Change in the output occurs when the state of the master is affected.

Q = ABC + AB + AB + AB
= ABC + AB (C + C) + AB (C + C) AB (C + C)
= ABC + ABC + ABC + ABC + ABC + ABC + ABC

In octal system
8⁰ = (1)₈
8¹ = (10)₈
8² = (100)₈
8³ = (1000)₈
8⁴ = (10000)₈

In successive approximation A/D converter, the conversion time is independent of theanalog input voltage. so, conversion time be 20 us.v

Generally square memory array is preferred because it requires less area for entire chip, as well as less number of address line to decode them

The smallest voltage increment
= 1 Percentage resolution x maximum value
= 1/2⁷ – 1 x 25.4 = 0.2 v

In straight binary code, let n be the minimum number of bits to encode
2ⁿ > 100
n = 7

Because of having highest noise margin HTL is most suitable in industrial environment.

In the ECL logic as the transistor is prevent from going into the saturation, therefore there is very low access time and high switching speed.

In ECL relatively higher power dissipation compared to the TTL or CMOS or DCTL logic gate family.

X = A * B
Y = A B
Z = C
Putting the different possibility F will be 1, if
A = 1, B = 0, C = 0

TTL stands for transistor-transistor logic and CMOS stands complementary metal oxide semiconductor.

Dividing 43 by 16
(43)₁₀ = (2B)₁₆
(43)₁₀ = (01000011)₂

the number of distinct boolean expressions of n-variables is 2²ⁿ
for n = 4,
distinct boolean expression = 2²⁴ = 65536.

the number of comparators required to built n-bit flash ADC is 2ⁿ – 1.
for n = 8,
number of comparators = 2⁸ – 1 = 255

output of TTl gate taken from BJT is in either totem pole or open collector configuration.

the output of first XOR gate
= A₁ = 1X + 0X = X
The output of second XOR gate
= A₂ = X X + XX
= X + X = 1
Again the input of third XOR gate 1 and X i.e., sequence repeat. hence, the output Y of 20 XOR gate is 1.

let us consider the following cases :
case I If Q = 0 then Q = 1
Then the sequence will be
000, 100, 110, 111, 011, 001, reqeat
Thus, there will be six states before repeating.
Case II if Q = 1 then Q = 0
then, the sequence will be
101, 010, repeat
Thus there will be two states before repeating
Hence, modulo cannot be determined usless the information about its initial state Q in not given.

Y = A [B + C(AB + AC)]
= A [B + C(AB . AC)]
= A [B + C(A + B).(A + C)]
= A [B + (AC + BC).(A + C)]
= A [B + AC + AC.C + ABC + BCC]
= A [B + AC + ABC] [ C.C = 0]
= A [B + AC (1 + B)]
= A [B + AC]
= AB + A.AC
= AB

For the circuit, initially Q₀ = Q₁ = 0. This a johnson counter as Q is feedback to input and a down counter and for a johnson counter the number of states
00, 10, 11, 01, 00, 10………
it will repeat after clock pulses. so after 776th clock pulse state is 00, as 774/4 = 194 and is remainder. hence, 777th clock pulse state is 10.

X = xyz + w x z + w yz
gate 1 gate 2 gate 3
by k-map simplification
X = xyz + wyz
hence, gate 2 is redundant.

Hence, the circuit will behave as a NOT gate.

Hence, after 5 states, the repeatition will start. thus, this is divide by 5 counter.

CMOS is slowest among the given logic family because of high input impedance.

In ECL, relatively higher power dissipation compared to the TTL or CMOS or DCTL logic gate family.

f (A , B, C, D)
= A’B’CD + A’BC’D + A’BCD + AB’C’D + AB’CD
0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1
3 5 7 9 11
f(A, B, C, D) = M (3, 5, 7, 9, 11)

f(A, B, C, D) = M(5, 9, 11, 14)
5 – 0101 – A’BC’D
9 – 1001 – AB’C’D
11 – 1011 – AB’CD
14 – 1110 – ABCD’
f(A, B, C, D) = A’BC’D + AB’C’D + AB’CD + ABCD’

f(A, B, C) = (A + B’ + C) (A’ + B’ + C) (A + B’ + C’)
A + B’ + C = 010 – 2
A’ + B’ + C = 110 – 6
A + B’ + C’ = 011 – 3
f(A, B, C) = IIM (2, 6, 3)
In terms of minterms
f(A, B, C) = M(0,1, 4, 5, 7)

f(A, B, C) = M(0, 1, 5, 7)
In terms of maxterms
f(A, B, C) = IIM (2, 3, 4, 6)

f(A, B, C) = IIM (0, 3, 5, 6)
In terms of minterms
f (A, B, C) = M(1, 2, 4, 7)

x(y + z) = xy + xz
applying dual theorem,
x + yz = (x + y) (x + z)

output at point a output at point a is the output of 10-bit ring counter and a ring counter is a N 1 divider where, N is number of bits so,
a = 100/10 = 10 kHz
output of point b
MOD-20 ripple counter is divided by 20 counter hence output at point b,
b = 10/20 = 500 Hz
output at point c
for 4-bit parallel counter, there will be 2⁴ = 16 stages so, number of c point
c = 500/16 = 31.25 Hz
output at point d
4-bit johnson counter is 2N : 1 divider, where N is the number of bit
d = 31.25/8 = 3.9 Hz

F₁ = A + B
F₃ = (A + B). C
F₂ = D . E
Y = F₂ . F₃ = F₂ + F₃
= D . E + (A + B) . C
= D . E + (A + B) C
= (A + B) C + DE

F₁ = AB
F₂ = CD
F₃ = EF
Y = F₁F₂F₃
Y = F₁ + F₂ + F₃
Y = AB + CD + EF

hence, this represents OR logic

PLA – contain programmable AND and OR gate.
PROM – contain programmable OR and fixed AND gate.

(FFF1)₁₆ = 1 x (16)⁰ + 15 x (16)¹ + 15 x (16)² + 15 x (16)³
(FFF1)₁₆ = 32767

In 2’s representation

maximum positive number that can be represented = + (2^n-1 – 1)
maximu negative number = – 2^n-1

In 1’s coplement representation
maximum positive number = + (2^n-1 – 1)
minimum positive number = – (2^n-1 – 1)

thus, the given CMOS satisfies the function of a positive NOR gate.

f(w, x, y, z) = (w + y). (w + x)

output = ABC + ABC + ABC + ABC
= C (AB + AB) + C (AB + AB)
= C (AB + AB) + C (AB + AB)
= A * B * C

f = D₈D₁ + D₄D₂D₁ + D₈D₄D₂D₁ + D₂D₁D₄

f(X₂, X₁, X₀) = M(0, 3, 6)
= IIM (1, 2, 4, 5, 7)

f₁ = D₀+ D₆ + D₄ + D₂
= D₀ + D₂ + D₄ + D₆
= M (0, 2, 4, 6)
and f₂ = D₅ + D₃ + D₁ + D₇
= M (1, 3, 5, 7)
So, f₁f₂ 0

in sign magnitude form
A = 00011110 = 30
B = 10011100
Because sign bit is 1 so, its decimal value will be
= – (2’s complement of 10011100)
= – (01100100)
= – 100

(177)₈ + 1 = (x)₈
(x)₈ = 1 x 8² + 7 x 8 + 7 x 8⁰ + 1
= 64 + 56 + 7 + 1
= (128)₁₀
it’s octal value can be calculated as
(128)₁₀ = (200)₈

the output X will be
X = D₆ + D₇ + D₅ + D₃
D₃ = 011 = ABC
D₅ = 101 = ABC
D₆ = 110 = ABC
D₇ = 111 = ABC
X = ABC + ABC + ABC + ABC
= (AB + AB) C + AB (C + C)
= (A * B) C + AB

so, can be written in the given form
S₀ = CB = 0.C
S₀ = CB = S₁
F = S₁A + S₁A
= CBA + CBA
= EX-OR gate

The output Z of the MUX will be
Z = S₁S₀X + S₁S₀1 + S₁S₀1 + S₁S₀Y
= YX + Y + 0 + 0
= YX + Y
= X + Y

output Y can be written in the SOP form as
Y = M(0, 3, 5, 6)
Y = ABC + ABC + ABC + ABC
= C (AB + AB) + C (AB + BA)
= C (A . B) C + (A . B)
= C (A * B) + C (A * B)
= A . B . C

output of the MUX will be
let us assume that that Z is taken as an input.
from the above figure, we conclude that
Z = M(0,1,2,5,8,12,13,15)
Now, we will minmize f by using k-map
Z = w x y + w x z + w x y + wxz + y zw
= w x y + w x y + wxz + y z w

resolution = V_FS/2^N-1
= 10.23/2¹⁰ – 1
= 10.23/1024-1 = 10.23/1023 = 0.01 V or 10 mV

= 2¹⁴ = 16 kb
memory = 16 kb
= 16 k x 8-bit
hence, number of chips required = 16k x 8/16k = 8

in successive approximation ADC conversion time does not depend upon the analog input signal. thus, the ime will be same 20 us for 1 V signal also.

the smallest incremental change in 1 V = 1/2^N
= 1/2¹⁰ = 1/1024
For 5 V
= 5 x 1/1024 = 5 mV

noise margin V_IH(MIN) given as
V_IH(MIN) = V_OH(MIN) – V_NL
= – 0.8 – 0.5
= – 1.3 V
and V_IL(MAX) = V_OL(MAX) + V_NH
= – 2 + 0.5
= – 1.5 V

resolution = V_FS/2^N – 1
50 x 10^-3 = 10/2ⁿ– 1
2ⁿ – 1 = 10 /50 x 10^-3 = 200
2ⁿ = 201
thus, 8-bit are required to coding the 201 levels.

Number of pins = 16 + 8 + 1 + 1 = 26

for a dual slope integrating ADC
V_ref x t₂ = v_int₁
and t₁ = 10/50 = 0.2 s
so, 2 x t₂ = 1 x 0.2
t₂ = 1 x 0.2/2
t₂ = 0.1 s

number of address bits required
2ⁿ = 2048
n = 11

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