the minimum number of 2-input nand gates required to implement the boolean function z=abc’ or A Boolean function Z = ABC is to be implement using NAND and NOR gate. each gate has unit cost. ?

**Common Data/Linked Answer Questions**

**Statements for Linked Answer Questions 1 and 2 **A Boolean function Z = ABC is to be implement using NAND and NOR gate. each gate has unit cost. only A, B and C are available.

- If both gate are available then minimum cost is

(a) 2 units

(b) 3 units

(c) 4 units

(d) 6 units

- If NAND gate are available then minimum cost is

(a) 2 units

(b) 3 units

(c) 4 units

(d) 6 units

**Statement for Linked Answer Questions 3, 4 and 5**

A MUX network is shown in figure.

- Z
_{1 }= ?

(a) a + b + c

(b) ab + ac + bc

(c) a . b . c

(d) a * b * c

- Z
_{2}= ?

(a) ab + bc + ca

(b) a + b + c

(c) abc

(d) a . b . c

- This circuit act as

(a) full adder

(b) half adder

(c) full subtractor

(d) half subtractor

**Common data for Questions 6 and 7 **

The building block shown in figure is a active high output decoder.

- The output X is

(a) AB + BC + CA

(b) A + B + C

(c) ABC

(d) none of these

- The output Y is

(a) A + B

(b) B + C

(c) C + A

(d) none of these

**Statements for linked answer questions 8 and 9**

A switching function of four variable, f(w,x,y,z) is equal to the product of two other function f_{1} and f_{2}, of the same variable f = f_{1}f_{2}. the function f and f_{1} are are follows :

f = m(4, 7, 15)

f_{1} = m (0,1,2,3,4,7,8,9,10,11,15)

- The number of full specified function, that will satisfy the given condition, is

(a) 32

(b) 16

(c) 4

(d) 1

- The simplest function for f
_{2}is

(a) x

(b) x

(c) y

(d) y

**Common data for Questions 10, 11 and 12**

A PLA realization is shown in figure.

- f
_{1}(x_{2},x_{1},x_{0}) = ?

(a) x_{2}x_{0} + x_{1}x_{0}

(b) x_{2}x_{0} + x_{1}x_{2}

(c) x_{2} * x_{0}

(d) x_{2} . x_{0}

- f
_{2}(x_{2},x_{1},x_{0}) = ?

(a) m (1,2,5,6)

(b) m (1,2,6,7)

(c) m (2,3,4)

(d) none of these

- f
_{3}(x_{2},x_{1},x_{0}) =?

(a) IIM (0,4,6,7)

(b) IIM (2,4,5,7)

(c) IIM (1,2,3,5)

(d) IIM (2,3,4,7)

**Statement for linked answer Questions 13 and 14**

Consider the circuit shown in figure.

- The expression for the next state Q
^{+ }is

(a) xQ

(b) xQ

(c) x * Q

(d) x uQ

- Let the clock pulses be numbered 1,2,3 ……after the point at which the flip-flop is reset (Q
_{0}= 0). The circuit is

(a) even parity checker

(b) odd parity genertor

(c) both (a) and (b)

(d) none of these

**Common data for Questions 15 and 16**

The 8-bit left shift register and D flip-flop shown in figure is synchronized with same clock. the D flip-flop is initially cleared.

- The circuit acts as

(a) binary to 2’s complement converter

(b) binary to gray code converter

(c) binary to 1’s complement converter

(d) binary to excess-3 code converter

- If initially register contains byte B7, then after 4 clock pulse contents of register will be

(a) 73

(b) 72

(c) 7E

(d) 74

**Statement for linked answer Questions 17 and 18**

A mealy system produces a 1 output if the input has been 0 for at least two consecutive clocks followed immediately by two or more consecutive 1’s.

- The minimum state for this system is

(a) 4

(b) 5

(c) 8

(d) 9

- The flip-flop required to implement this system are

(a) 2

(b) 3

(c) 4

(d) 5

**Statements for linked Answer Questions 19 and 20**

Two products are sold from a vendingmachine, which has two push buttons p_{1 }and p_{2}. when a button is pressed, the price of the corresponding products is displayed in a 7-segment display.

If no buttons are pressed, 2 is displayed, signifying 0.

If only p_{1} is pressed, 2 is displayed signifying 2.

If only p_{2} is pressed, 5 is displayed, signifying 5.

If both p_{1} and p_{2} are pressed, E is displayed, signifying error.

The names of the segments in the 7-segment display k, and the glow of the display for 0,2,5 and E are shown below.

**Consider**

(i) push button pressed/not pressed is equivalent to logic 1/0 respectively.

(ii) A segment glowing/not glowing in the display is equivalent to logic 1/0 respectively.

- If segments a to g are considered as function of p
_{1}and p_{2}then which of the following is correct?

(a) q = p_{1} + p_{2}, d = c +e

(b) g = p_{1} + p_{2}, d = c + e

(c) q = p_{1} + p_{2}, e = b + c

(d) g = p_{1} + p_{2}, e = b + c

- What are the minimum numbers of NOT gates and 2-input OR gates required to design the logic of the driver for this 7-segment display?

(a) 3 NOT and 4 OR

(b) 2 NOT and 4 OR

(c) 1 NOT and 3 OR

(d) 2 NOT and 3 OR

**Statements for linked Answer Questions 21 and 22**

In the following circuit, the comparator output is logic 1 if V_{1} > V_{2} and is logic 0 otherwise, the D/A conversion is done as per the relations.

V_{DAC} = 3 2^{N-2} V, where b_{3}(MSB), b_{2} , b_{1} and b_{0} (LSB) are the counter outputs. the counter starts from the clear state.

- The stable reading of the LED display is

(a) 06

(b) 07

(c) 12

(d) 13

- The magnitude of the error between V
_{DAC}and V_{IN}at steady state in volt is

(a) 0.2

(b) 0.3

(c) 0.5

(d) 1.0

**Common data for Questions 23 and 24**

Consider the resistor transistor logic gate of figure

- For positive logic the gate is

(a) AND

(b) OR

(c) NAND

(d) NOR

- For negative logic the gate is

(a) AND

(b) OR

(c) NAND

(d) NOR

**Common data for Questions 25 and 26**

Consider the DL circuit of figure

- For positive logic, the circuit is a

(a) AND

(b) OR

(c) NAND

(d) NOR

- For negative logic, the circuit is a

(a) AND

(b) OR

(c) NAND

(d) NOR

**Statement for linked Answer Questions 27 and 28**

The input-output voltage specification for the standard TTL family are as follows V_{OH(MIN) } = 2.4 V, V_{OL(MAX)} = 0.4 V, V_{IH(MIN)} = 2.0 V and V_{IL(MAX)} = 0.8 V

- The maximum-amplitude nose spike, that can be tolerated when a high input is driving an input, is

(a) 0.4 V

(b) 0.8 V

(c) 0.2 V

(d) 0.6 V

- The maximum-amplitude noise spike, that can be tolerated wnen a low output is driving an input, is

(a) 0.4 V

(b) 0.8 V

(c) 0.2 V

(d) 0.6 V

**Common data for Qeuestions 29 and 30**

Consider the RTL circuit of figure :

- If V
_{OT}is taken as the output, then circuit is a

(a) AND

(b) OR

(c) NAND

(d) NOR

- If V
_{02}is taken as the output, then circuit is a

(a) AND

(b) OR

(c) NAND

(d) NOR

**Common data for Questions 31 and 32**

Consider the circuit of figure

- If V
_{O1}is taken as the output, the logic is

(a) AND

(b) OR

(c) NAND

(d) NOR

- If V
_{02}is taken as the output, the logic is

(a) AND

(b) OR

(c) NAND

(d) NOR

**Statements for linked Answer Questions 33, 34 and 35**

Consider the AND circuit shown in figure. the binary input levels are V(0) V and V(1) = 25 V. Assume ideal diodes, if V_{1} = V(0) and V_{2} = V(1), then V_{0} is to be at 5V. However if V_{1} = V_{2} = V(1), then V_{0} is to rise above 5 V.

- If V
_{SS}= 20 V and V_{1}= V_{2}= V(1), The diode current I_{DI}, I_{D2}and D_{00}are

(a) 1 mA, 1 mA, 4 mA

(b) 1 mA, 1 mA, 5 mA

(c) 5 mA, 5 mA, 1 mA

(d) 0, 0, 0

- If V
_{SS}= 40 V and both input are at high level then, diode current I_{D1}, I_{D2}and I_{D0}are respectively

(a) 0.4 mA, 0.4 mA, 0

(b) 0,0, 1 mA

(c) 0.4 mA, 0.4 mA, 1 mA

(d) 0, 0, 0

- The maximum value of V
_{SS}which may be used is

(a) 30 v

(b) 25 v

(c) 125 v

(d) 20 v

**Statement for linked Answer Questions 36, 37, and 38**

- When a 74LS device is driving 74ALS input, the noise margins V
_{NH}and V_{NL}are respectively,

(a) 0.2 v, 0.3 v

(b) 0.3 v, 0.2 v

(c) 0.7 v, 0.3 v

(d) 0.3 v, 0.7 v

- When a 74ALS device is driving a 74LS input, the noise margin V
_{NH}and V_{NL}are respectively

(a) 0.4 v, 0.5 v

(b) 0.5 v, 0.4 v

(c) 0.3 v, 0.7 v

(d) 0.7 v, 0.3 v

- If circuit uses 74LS and 74ALS in combination, then overall noise margin V
_{NH}and V_{NL}are respectively,

(a) 0.4 v, 0.7 v

(b) 0.7 v, 0.4 v

(c) 0.3 v, 0.5 v

(d) 0.5 v 0.3 v

**Common data for Questions 39 and 40**

in the circuit of figure each gate is a 74LS series device with I_{IH} = 20 uA and I_{IL} = 0.4 mA

- In high state, the loading on the output of gate 1 is

(a) 2.4 mA

(b) 120 uA

(c) 60 uA

(d) 1.2 mA

- In low state, the loading on the output of gate 1 is

(a) 0.8 mA

(b) 1.2 mA

(c) 2.0 mA

(d) 2.4 mA

**Common data for Questions 41 and 42**

Consider the TTL circuit of figure. if either or both V_{1} and V_{2} are logic low, Q_{1} is driven to saturation.

- The output V
_{01}produces logic

(a) AND

(b) OR

(c) NAND

(d) NOR

- The output V
_{02}produces logic

(a) AND

(b) OR

(c) NAND

(d) NOR

**Statement for linked Answer Questions 43 and 44**

In the digital to analog converter circuit shown in the figure below, V_{R} = 10 V and R = 10 K

- The current I is

(a) 31.25 uA

(b)62.5 uA

(c) 125 uA

(d) 250 uA

- The voltage V
_{0}is

(a) -0.781 v

(b) -1.562 v

(c) -3.125 v

(d) -6.250 v

**Common data for Questions 45 and 46**

- The value of V
_{OUT}for an input code of 10110011 would be

(a) 4.28 v

(b) 3.96 v

(c) 4.56 v

(d) 3.58 v

- The resolution of the DAC is

(a) 0.1%

(b) 0.3%

(c) 0.2%

(d) 0.4%

**Common Data/linked Answer Questions **

- (a) Boolean function

Z = ABC

= ABC = ABC = AC + B

Therefore one NAND and one NOR gate is required so, the cost will be 2 unit.

- (a)

Converting the logic into NAND gate logic

Hence 4 units are required to made a NOR.

- (d)

The output of first MUX is

Z_{O} = ab + ab = a * b

The output of first MUX work as a select line for both of the second level MUX, so

S_{O} = a * b

and _{ }Z_{1} = S_{0} c + S_{O}c

= a * b . c + a * b . c

= (a * b) . c + (a * b) . c

Z_{1} = (a * b * c)

- (a)

Z_{2} = BS_{O} + cS_{0}

= b(ab + ab) + c(ab + ab) = ab + abc + abc

= a(b + bc) + abc = ab + ac + abc

= ab + ac + bc

- (a)

output of the first, second level MUX represents the equation of sum of A and B with carry and equation of the second is the resultant carry. thus, this represents a full adder.

- (a)

The output

X = D_{6} + D_{7} + D_{5} + D_{3}

= D_{3} + D_{5} + D_{6} + D_{7}

= ABC + ABC + ABC + ABC

X = AC + AB + BC

- (d)

Y = D_{3} + D_{5} + D_{1} + D_{1}

= D_{1} + D_{3} + D_{5} + D_{7}

= M (1, 3, 5, 7)

Y = C

- (a)

f_{1} = m (1,2,3,4,7,8,9,10,11,15)

f = m(4,7,15)

f = f_{1}f_{2}

f_{2} = m(4, 7, 15) + d(5, 6, 12, 13, 14)

Because there are 5 don’t care conditions.

so, 2^{5} = 32 different functions f_{2}.

- (a)

f_{2} = m(4, 7, 15) + dc(5, 6 12, 13, 14)

f_{2} = x

- (c)

f_{1} = x_{0}x_{2} + x_{0}x_{1}x_{2} + x_{0}x_{2}

= x_{0}x_{2} (1 + x_{1}) + x_{0}x_{2} [(1 + x_{1}) = 1]

= x_{0}x_{2} + x_{0}x_{2}

= x_{0} * x_{2}

- (b)

f_{2} = x_{0}x_{1} + x_{1}x_{2} + x_{0}x_{1}x_{2}

= x_{0}x_{1}x_{2} + x_{0}x_{1}x_{2} + x_{1}x_{2}x_{0} + x_{1}x_{2}x_{0} + x_{0}x_{1}x_{2}

= x_{2}x_{1}x_{0} + x_{2}x_{1}x_{0} + x_{2}x_{1}x_{0} + x_{2}x_{1}x_{0} [x_{2}x_{1}x_{0} + x_{2}x_{1}x_{0} = x_{2}x_{1}x_{0}]

f_{2}(x_{2},x_{1},x_{0}) = m(1, 2, 6,7)

- (c)

f_{3} = x_{0}x_{1} + x_{1}x_{2}

= x_{2}x_{1}x_{0} + x_{2}x_{1}x_{0} + x_{2}x_{1}x_{0} + x_{2}x_{1}x_{0}

f_{3}(x_{2} x_{1} x_{0}) = m(0, 4, 6, 7)

f_{3}(x_{2} x_{1} x_{0}) = IIM(1,2,3,5)

- (c)

Truth table for next state Q^{+}

Q^{+} = xQ + xQ

Q^{+} = x * Q

- (d)

Next state is given as

Q^{+} = x * Q

Q^{+}_{1} = x_{1} * Q_{0} = x_{1}0 + x_{1}0 = x_{1}

Q_{2}^{+} = x_{2} * x_{1}, Q^{+}_{3} = x_{3} * x_{2} * x_{1}

Q_{4}^{+ }= x_{4} * x_{3} * x_{2} * x_{1}

so, this circuit is used to generate even parit and for checking odd parity.

- (b)

let initially Q = 0, and the output of the XOR gate is Y.

after first clock

Y = B_{7} * 0 = B_{7}

after second clock

Y = B_{7} * B_{6}

After third clock

Y = B_{7} *B_{5}

After fourth clock

Y = B_{5} * B_{4}

Hence, this circuit will work as a binary to gray code converter.

- (c)

if register contain byte B7 then,

B7 = 10110111

After first clock pulse

Y = B_{7} * 0 = 1 * 0 = 1 B’_{3}

After second clock pulse

Y = B_{7} * B_{6} = 1 * 0 = 1 = B_{2}

After third clock pulse

Y = B_{6} * B_{5} = 0 * 1 = 1 = B’_{1}

After fourth clock pulse

Y = B_{5} * B_{4} = 1 * 1 = 0 B’_{0}

Where b’_{3} b’_{2} b’_{1} b’_{0} are the new values of b_{3} b_{2} b_{1} b_{0} After shifting.

so, output of the shift register

01111110_{2} = 7E_{16}

- (a)

the state diagram of mealy system is shown below.

so, there are four minimum states.

- (a)

2^{n} = 4

n = 2

thus, two flip-flops are required.

- (b)

As per question, the truth table.

hence,

a = 1

b = p_{1}p_{2} + p_{1}p_{2} = p_{2}(p_{1} + p_{1}) = p_{2}

c = p_{1}p_{2} + p_{1}p_{2} = p_{1}(p_{2} + p_{2}) = p_{1}

d = 1

e = p_{1}p_{2} = p_{1} + p_{2}

f = p_{1}p_{2} = p_{1} + p_{2}

g = p_{1}p_{2} = p_{1} + p_{2}

- (d)

a = 1

b = p_{2} = 1 NOT gate required

c = p_{1} = 1 NOT gate required

e = p_{1} + p_{2} = 1 NOR gate required

f = P_{1} + P_{2} = 1 OR gate required

g = P_{1} + P_{2} = 1 OR gate required

hence, 2 NOT and 3 OR gates required.

- (d)

V_{DAC} + 2^{-1}B_{0} + 2^{0}B_{1} + 2^{1}B_{2} + 2^{2}B_{3}

When V_{DAC} = 6.5 V

The output of AND is zero and hence stable output is 13.

- (b)

error = V_{DAC} – V_{IN} = 6.5 – 6.2 = 0.3 V

- (d)
- (c)

when negative logic is used the circuit represents NAND gate function.

- (a)

for positive logic

so, the circuit will be an AND gate.

- (b)

for negative logic

so, the circuit will be an OR gate for a negative logic.

- (a)

A negative noise splike that can drive the actual voltage below 2.0 v if its amplitude is greater than

V_{NH} = V_{OH(MIN)} – V_{IH(MIN)}

= 2.4 – 2.0

= 0.4 V

- (a)

A positve noise spike can drive the actual voltage above the 0.8 v level if its aplitude is greater than

V_{NL} = V_{IL(MAX)} – V_{OL(MAX)}

= 0.8 – 0.4

= 0.4 V

- (d)

this truth table shown NOR logic.

- (b)

the output V_{02} is the logic complement of V_{01}

Therefore, this is a OR gate.

- (c)

thus the truth table shows NAND logic.

- (a)

The Q_{3} state is simple an inverter. hence AND logic is represented.

- (d)

all diodes are in reverse bias hence all diode current are zero.

- (a)

because V(1) = 25 V, so diode D_{1} and D_{2} will be on and D_{0 } will be off. so, I_{D1} and I_{D2} will be equal and I_{D0} will be zero.

calculation of I_{D1} and I_{D2}

V_{A} = 25 x 20/20.5 + 40 x 05/20.5 = 25.4 v

I_{D1} = I_{D2} = 25.4 – 25/1 x 10^{3}

= 0.4 mA

l_{d1} = 0.4 mA

I_{D2} = 0.4 mA

I_{D0} = 0

- (c)

when V_{1} = V (0)

V_{2} = V(1)

V_{0} = 5 V

Assume D_{1} = On D_{2} = Off D_{0} = On D_{2} is reveres biased by 20 v. hence it is off D_{2} is forward biased by 5 v. hence, it is on, to have D_{0} On I_{D0} must be greater than 0.

I_{D0 }= – (V_{SS} – 5)/20K + 5 – 0/1 K > 0

-V_{SS} + 5 + 120 > 0

V_{SS} < 125 V

- (c)

because 74LS device is driving the 74ALS so,

- (c)

because 74LS device is driving the 74ALS so, the noise margin will be calculated as V_{NH}.

V_{NH} = V_{OH(MIN)} – V_{IH(MIN)}

= 2.7 – 2.0

= 0.7 V

V_{NL} = V_{IL(MAX) }– V_{OL(MAX)}

= 0.8 – 0.4 = 0.4 V

- (b)

when 74ALS device is driving 74LS the, noise margin will be

V_{NH} = V_{OH(MIN)} – V_{IH(MIN)}

= 2.5 – 2 = 0.5 V

V_{NL} = V_{IL(MAX) }– V_{OL(MAX)}

= 0.8 – 0.4 = 0.4 V

- (d)

when circuit usee 74LS and 74ALS in combination then,

overall noise margin V_{NH} = 0.5 V

V_{NL} = 0.3 V

- (b)

because output of gate 1 drives the six input of the next level gates. so, in high state the loading is equivalent to six 74LS input load therefore.

load = 6 x I_{IH}

= 6 x 20 u = 120 uA

- (c)

The truth table for various combinations of V_{1} and V_{2}

The truth table represents AND logic

- (c)

the Q_{2} stage is simply an inverter. therefore, the output V_{02} is the logic complement of V_{01}.

- (b)

from concept of virtual ground V_{A} = 0 (Grounded)

henec, current from voltage source

I = V_{R}/R = 10/10 x10^{3} = 1 mA

due to symmetry in the branches of circuit, the current division among various branches is

hence, current = I/16 A = 1 mA/16 = 62.5 uA

- (c)

the voltage V_{O} = – I_{O}R

= – (I/16 + I/4)R

= – (5I/16)R

= – 5 x 1 mA x 10 k/16 = – 3.125 v

- (d)

input output

01100100_{2} = 100_{10} 2.0 v

10110011_{2} = 179_{10} (x)

x/2 = 179/100

x = 3.58 v

- (d)

resoltuion = V_{FS}/2^{N} – 1 x 100

1/2^{8} – 1 x 100 = 0.4 %