the minimum number of 2-input nand gates required to implement the boolean function z=abc’ or A Boolean function Z = ABC is to be implement using NAND and NOR gate. each gate has unit cost. ?
Statements for Linked Answer Questions 1 and 2    A Boolean function Z = ABC is to be implement using NAND and NOR gate. each gate has unit cost. only A, B and C are available.

1. If both gate are available then minimum cost is

(a) 2 units
(b) 3 units
(c) 4 units
(d) 6 units

1. If NAND gate are available then minimum cost is

(a) 2 units
(b) 3 units
(c) 4 units
(d) 6 units
A MUX network is shown in figure.

1. Z1 = ?

(a) a + b + c
(b) ab + ac + bc
(c) a . b . c
(d) a * b * c

1. Z2 = ?

(a) ab + bc + ca
(b) a + b + c
(c) abc
(d) a . b . c

1. This circuit act as

(c) full subtractor
(d) half subtractor
Common data for Questions 6 and 7
The building block shown in figure is a active high output decoder.

1. The output X is

(a) AB + BC + CA
(b) A + B + C
(c) ABC
(d) none of these

1. The output Y is

(a) A + B
(b) B + C
(c) C + A
(d) none of these
A switching function of four variable, f(w,x,y,z) is equal to the product of two other function f1 and f2, of the same variable f = f1f2. the function f and f1 are are follows :
f = m(4, 7, 15)
f1 = m (0,1,2,3,4,7,8,9,10,11,15)

1. The number of full specified function, that will satisfy the given condition, is

(a) 32
(b) 16
(c) 4
(d) 1

1. The simplest function for f2 is

(a) x
(b) x
(c) y
(d) y
Common data for Questions 10, 11 and 12
A PLA realization is shown in figure.

1. f1(x2,x1,x0) = ?

(a) x2x0 + x1x0
(b) x2x0 + x1x2
(c) x2 * x0
(d) x2 . x0

1. f2 (x2,x1,x0) = ?

(a) m (1,2,5,6)
(b) m (1,2,6,7)
(c) m (2,3,4)
(d) none of these

1. f3 (x2,x1,x0) =?

(a) IIM (0,4,6,7)
(b) IIM (2,4,5,7)
(c) IIM (1,2,3,5)
(d) IIM (2,3,4,7)
Consider the circuit shown in figure.

1. The expression for the next state Q+ is

(a) xQ
(b) xQ
(c) x * Q
(d) x uQ

1. Let the clock pulses be numbered 1,2,3 ……after the point at which the flip-flop is reset (Q0 = 0). The circuit is

(a) even parity checker
(b) odd parity genertor
(c) both (a) and (b)
(d) none of these
Common data for Questions 15 and 16
The 8-bit left shift register and D flip-flop shown in figure is synchronized with same clock. the D flip-flop is initially cleared.

1. The circuit acts as

(a) binary to 2’s complement converter
(b) binary to gray code converter
(c) binary to 1’s complement converter
(d) binary to excess-3 code converter

1. If initially register contains byte B7, then after 4 clock pulse contents of register will be

(a) 73
(b) 72
(c) 7E
(d) 74
A mealy system produces a 1 output if the input has been 0 for at least two consecutive clocks followed immediately by two or more consecutive 1’s.

1. The minimum state for this system is

(a) 4
(b) 5
(c) 8
(d) 9

1. The flip-flop required to implement this system are

(a) 2
(b) 3
(c) 4
(d) 5
Two products are sold from a vendingmachine, which has two push buttons p1 and p2. when a button is pressed, the price of the corresponding products is displayed in a 7-segment display.
If no buttons are pressed, 2 is displayed, signifying 0.
If only p1 is pressed, 2 is displayed signifying 2.
If only p2 is pressed, 5 is displayed, signifying 5.
If both p1 and p2 are pressed, E is displayed, signifying error.
The names of the segments in the 7-segment display k, and the glow of the display for 0,2,5 and E are shown below.
Consider
(i) push button pressed/not pressed is equivalent to logic 1/0 respectively.
(ii) A segment glowing/not glowing in the display is equivalent to logic 1/0 respectively.

1. If segments a to g are considered as function of p1 and p2 then which of the following is correct?

(a) q = p1 + p2, d = c +e
(b) g = p1 + p2, d = c + e
(c) q = p1 + p2, e = b + c
(d) g = p1 + p2, e = b + c

1. What are the minimum numbers of NOT gates and 2-input OR gates required to design the logic of the driver for this 7-segment display?

(a) 3 NOT and 4 OR
(b) 2 NOT and 4 OR
(c) 1 NOT and 3 OR
(d) 2 NOT and 3 OR
In the following circuit, the comparator output is logic 1 if V1 > V2 and is logic 0 otherwise, the D/A conversion is done as per the relations.
VDAC = 3  2N-2 V, where b3(MSB), b2 , b1 and b0 (LSB) are the counter outputs. the counter starts from the clear state.

1. The stable reading of the LED display is

(a) 06
(b) 07
(c) 12
(d) 13

1. The magnitude of the error between VDAC and VIN at steady state in volt is

(a) 0.2
(b) 0.3
(c) 0.5
(d) 1.0
Common data for Questions 23 and 24
Consider the resistor transistor logic gate of figure

1. For positive logic the gate is

(a) AND
(b) OR
(c) NAND
(d) NOR

1. For negative logic the gate is

(a) AND
(b) OR
(c) NAND
(d) NOR
Common data for Questions 25 and 26
Consider the DL circuit of figure

1. For positive logic, the circuit is a

(a) AND
(b) OR
(c) NAND
(d) NOR

1. For negative logic, the circuit is a

(a) AND
(b) OR
(c) NAND
(d) NOR
The input-output voltage specification for the standard TTL family are as follows VOH(MIN)  = 2.4 V, VOL(MAX) = 0.4 V, VIH(MIN) = 2.0 V and VIL(MAX) = 0.8 V

1. The maximum-amplitude nose spike, that can be tolerated when a high input is driving an input, is

(a) 0.4 V
(b) 0.8 V
(c) 0.2 V
(d) 0.6 V

1. The maximum-amplitude noise spike, that can be tolerated wnen a low output is driving an input, is

(a) 0.4 V
(b) 0.8 V
(c) 0.2 V
(d) 0.6 V
Common data for Qeuestions 29 and 30
Consider the RTL circuit of figure :

1. If VOT is taken as the output, then circuit is a

(a) AND
(b) OR
(c) NAND
(d) NOR

1. If V02 is taken as the output, then circuit is a

(a) AND
(b) OR
(c) NAND
(d) NOR
Common data for Questions 31 and 32
Consider the circuit of figure

1. If VO1 is taken as the output, the logic is

(a) AND
(b) OR
(c) NAND
(d) NOR

1. If V02 is taken as the output, the logic is

(a) AND
(b) OR
(c) NAND
(d) NOR
Consider the AND circuit shown in figure. the binary input levels are V(0) V and V(1) = 25 V. Assume ideal diodes, if V1 = V(0) and V2 = V(1), then V0 is to be at 5V. However if V1 = V2 = V(1), then V0 is to rise above 5 V.

1. If VSS = 20 V and V1 = V2 = V(1), The diode current IDI, ID2 and D00 are

(a) 1 mA, 1 mA, 4 mA
(b) 1 mA, 1 mA, 5 mA
(c) 5 mA, 5 mA, 1 mA
(d) 0, 0, 0

1. If VSS = 40 V and both input are at high level then, diode current ID1, ID2 and ID0 are respectively

(a) 0.4 mA, 0.4 mA, 0
(b) 0,0, 1 mA
(c) 0.4 mA, 0.4 mA, 1 mA
(d) 0, 0, 0

1. The maximum value of VSS which may be used is

(a) 30 v
(b) 25 v
(c) 125 v
(d) 20 v

1. When a 74LS device is driving 74ALS input, the noise margins VNH and VNL are respectively,

(a) 0.2 v, 0.3 v
(b) 0.3 v, 0.2 v
(c) 0.7 v, 0.3 v
(d) 0.3 v, 0.7 v

1. When a 74ALS device is driving a 74LS input, the noise margin VNH and VNL are respectively

(a) 0.4 v, 0.5 v
(b) 0.5 v, 0.4 v
(c) 0.3 v, 0.7 v
(d) 0.7 v, 0.3 v

1. If circuit uses 74LS and 74ALS in combination, then overall noise margin VNH and VNL are respectively,

(a) 0.4 v, 0.7 v
(b) 0.7 v, 0.4 v
(c) 0.3 v, 0.5 v
(d) 0.5 v 0.3 v
Common data for Questions 39 and 40
in the circuit of figure each gate is a 74LS series device with IIH = 20 uA and IIL = 0.4 mA

1. In high state, the loading on the output of gate 1 is

(a) 2.4 mA
(b) 120 uA
(c) 60 uA
(d) 1.2 mA

1. In low state, the loading on the output of gate 1 is

(a) 0.8 mA
(b) 1.2 mA
(c) 2.0 mA
(d) 2.4 mA
Common data for Questions 41 and 42
Consider the TTL circuit of figure. if either or both V1 and V2 are logic low, Q1 is driven to saturation.

1. The output V01 produces logic

(a) AND
(b) OR
(c) NAND
(d) NOR

1. The output V02 produces logic

(a) AND
(b) OR
(c) NAND
(d) NOR
In the digital to analog converter circuit shown in the figure below, VR = 10 V and R = 10 K

1. The current I is

(a) 31.25 uA
(b)62.5 uA
(c) 125 uA
(d) 250 uA

1. The voltage V0 is

(a) -0.781 v
(b) -1.562 v
(c) -3.125 v
(d) -6.250 v
Common data for Questions 45 and 46

1. The value of VOUT for an input code of 10110011 would be

(a) 4.28 v
(b) 3.96 v
(c) 4.56 v
(d) 3.58 v

1. The resolution of the DAC is

(a) 0.1%
(b) 0.3%
(c) 0.2%
(d) 0.4%

1. (a) Boolean function

Z = ABC
= ABC = ABC = AC + B
Therefore one NAND and one NOR gate is required so, the cost will be 2 unit.

1. (a)

Converting the logic into NAND gate logic
Hence 4 units are required to made a NOR.

1. (d)

The output of first MUX is
ZO = ab + ab = a * b
The output of first MUX work as a select line for both of the second level MUX, so
SO = a * b
and   Z1 = S0 c + SOc
= a * b . c + a * b . c
= (a * b) . c + (a * b) . c
Z1 = (a * b * c)

1. (a)

Z2 = BSO + cS0
= b(ab + ab) + c(ab + ab) = ab + abc + abc
= a(b + bc) + abc = ab + ac + abc
= ab + ac + bc

1. (a)

output of the first, second level MUX represents the equation of sum of A and B with carry and equation of the second is the resultant carry. thus, this represents a full adder.

1. (a)

The output
X = D6 + D7 + D5 + D3
= D3 + D5 + D6 + D7
= ABC + ABC + ABC + ABC
X = AC + AB + BC

1. (d)

Y = D3 + D5 + D1 + D1
= D1 + D3 + D5 + D7
= M (1, 3, 5, 7)
Y = C

1. (a)

f1 = m (1,2,3,4,7,8,9,10,11,15)
f = m(4,7,15)
f = f1f2
f2 = m(4, 7, 15) + d(5, 6, 12, 13, 14)
Because there are 5 don’t care conditions.
so, 25 = 32 different functions f2.

1. (a)

f2 = m(4, 7, 15) + dc(5, 6 12, 13, 14)
f2 = x

1. (c)

f1 = x0x2 + x0x1x2 + x0x2
= x0x2 (1 + x1) + x0x2            [(1 + x1) = 1]
= x0x2 + x0x2
= x0 * x2

1. (b)

f2 = x0x1 + x1x2 + x0x1x2
= x0x1x2 + x0x1x2 + x1x2x0 + x1x2x0 + x0x1x2
= x2x1x0 + x2x1x0 + x2x1x0 + x2x1x0          [x2x1x0 + x2x1x0 = x2x1x0]
f2(x2,x1,x0) = m(1, 2, 6,7)

1. (c)

f3 = x0x1 + x1x2
= x2x1x0 + x2x1x0 + x2x1x0 + x2x1x0
f3(x2 x1 x0) = m(0, 4, 6, 7)
f3(x2 x1 x0) = IIM(1,2,3,5)

1. (c)

Truth table for next state Q+
Q+ = xQ + xQ
Q+ = x * Q

1. (d)

Next state is given as
Q+ = x * Q
Q+1 = x1 * Q0 = x10 + x10 = x1
Q2+ = x2 * x1, Q+3 = x3 * x2 * x1
Q4+ = x4 * x3 * x2 * x1
so, this circuit is used to generate even parit and for checking odd parity.

1. (b)

let initially Q = 0, and the output of the XOR gate is Y.
after first clock
Y = B7 * 0 = B7
after second clock
Y = B7 * B6
After third clock
Y = B7 *B5
After fourth clock
Y = B5 * B4
Hence, this circuit will work as a binary to gray code converter.

1. (c)

if register contain byte B7 then,
B7 = 10110111
After first clock pulse
Y = B7 * 0 = 1 * 0 = 1 B’3
After second clock pulse
Y = B7 * B6 = 1 * 0 = 1 = B2
After third clock pulse
Y = B6 * B5 = 0 * 1 = 1 = B’1
After fourth clock pulse
Y = B5 * B4 = 1 * 1 = 0 B’0
Where b’3 b’2 b’1 b’0 are the new values of b3 b2 b1 b0 After shifting.
so, output of the shift register
011111102 = 7E16

1. (a)

the state diagram of mealy system is shown below.
so, there are four minimum states.

1. (a)

2n = 4
n = 2
thus, two flip-flops are required.

1. (b)

As per question, the truth table.
hence,
a = 1
b = p1p2 + p1p2 = p2(p1 + p1) = p2
c = p1p2 + p1p2 = p1(p2 + p2) = p1
d = 1
e = p1p2 = p1 + p2
f  = p1p2 = p1 + p2
g = p1p2 = p1 + p2

1. (d)

a = 1
b = p2 = 1 NOT gate required
c = p1 = 1 NOT gate required
e = p1 + p2 = 1 NOR gate required
f = P1 + P2 = 1 OR gate required
g = P1 + P2 = 1 OR gate required
hence, 2 NOT and 3 OR gates required.

1. (d)

VDAC + 2-1B0 + 20B1 + 21B2 + 22B3
When VDAC = 6.5 V
The output of AND is zero and hence stable output is 13.

1. (b)

error = VDAC – VIN = 6.5 – 6.2 = 0.3 V

1. (d)
2. (c)

when negative logic is used the circuit represents NAND gate function.

1. (a)

for positive logic
so, the circuit will be an AND gate.

1. (b)

for negative logic
so, the circuit will be an OR gate for a negative logic.

1. (a)

A negative noise splike that can drive the actual voltage below 2.0 v if its amplitude is greater than
VNH = VOH(MIN) – VIH(MIN)
= 2.4 – 2.0
= 0.4 V

1. (a)

A positve noise spike can drive the actual voltage above the 0.8 v level if its aplitude is greater than
VNL = VIL(MAX) – VOL(MAX)
= 0.8 – 0.4
= 0.4 V

1. (d)

this truth table shown NOR logic.

1. (b)

the output V02 is the logic complement of V01
Therefore, this is a OR gate.

1. (c)

thus the truth table shows NAND logic.

1. (a)

The Q3 state is simple an inverter. hence AND logic is represented.

1. (d)

all diodes are in reverse bias hence all diode current are zero.

1. (a)

because V(1) = 25 V, so diode D1 and D2 will be on and D0  will be off. so, ID1 and ID2 will be equal and ID0 will be zero.
calculation of ID1 and ID2
VA = 25 x 20/20.5 + 40 x 05/20.5 = 25.4 v
ID1 = ID2 = 25.4 – 25/1 x 103
= 0.4 mA
ld1 = 0.4 mA
ID2 = 0.4 mA
ID0 = 0

1. (c)

when  V1 = V (0)
V2 = V(1)
V0 = 5 V
Assume D1 = On D2 = Off D0 = On D2 is reveres biased by 20 v. hence it is off D2 is forward biased by 5 v. hence, it is on, to have D0 On ID0 must be greater than 0.
ID0 = – (VSS – 5)/20K + 5 – 0/1 K > 0
-VSS + 5 + 120 > 0
VSS < 125 V

1. (c)

because 74LS device is driving the 74ALS so,

1. (c)

because 74LS device is driving the 74ALS so, the noise margin will be calculated as VNH.
VNH = VOH(MIN) – VIH(MIN)
= 2.7 – 2.0
= 0.7 V
VNL = VIL(MAX) – VOL(MAX)
= 0.8 – 0.4 = 0.4 V

1. (b)

when 74ALS device is driving 74LS the, noise margin will be
VNH = VOH(MIN) – VIH(MIN)
= 2.5 – 2 = 0.5 V
VNL = VIL(MAX)  – VOL(MAX)
= 0.8 – 0.4 = 0.4 V

1. (d)

when circuit usee 74LS and 74ALS in combination then,
overall noise margin VNH = 0.5 V
VNL = 0.3 V

1. (b)

because output of gate 1 drives the six input of the next level gates. so, in high state the loading is equivalent to six 74LS input load therefore.
= 6 x 20 u = 120 uA

1. (c)

The truth table for various combinations of V1 and V2
The truth table represents AND logic

1. (c)

the Q2 stage is simply an inverter. therefore, the output V02 is the logic complement of V01.

1. (b)

from concept of virtual ground VA = 0 (Grounded)
henec, current from voltage source
I = VR/R = 10/10 x103 = 1 mA
due to symmetry in the branches of circuit, the current division among various branches is
hence, current = I/16 A = 1 mA/16 = 62.5 uA

1. (c)

the voltage VO = – IOR
= – (I/16 + I/4)R
= – (5I/16)R
= – 5 x 1 mA x 10 k/16 = – 3.125 v

1. (d)

input                         output
011001002 = 10010       2.0 v
101100112 = 17910       (x)
x/2  = 179/100
x = 3.58 v

1. (d)

resoltuion = VFS/2N – 1 x 100
1/28 – 1 x 100 = 0.4 %