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**Combinational logic Circuit **

**combinational logic circuit** A combinational logic circuit consists of logic gates whose outputs at any time are determined from only the present combination of inputs.

**Arithmetic Circuits **Arithmetic circuits are used to perform addition and subtraction. binary adder performs binary addition. Adders and subtractors are classified into two categories.

Classification of adder

- Half adder
- Full adder

Classification of Subtractor

- Half subtractor
- Full subtractor

**Half Adder**

It is used to perform the addition of single bit. half adder contains two input lines for input data and two output lines for sum output and carry output.

**Logic Diagram**

We obtain the logic circuits as shown for the sum and carry expression

Sum (s) = AB + AB = A * B

Carry (c) = AB

**Full Adder**

A full adder is a combinational logic circuit that performs the arithmetic sum of three input bits. it consists of three inputs and two outputs.

**Truth Table **

From the truth table

S = ABC_{i} + ABC_{I} + ABC_{I} + ABC_{I} = A * B * C

C_{o} = AB + BC_{I} + AC_{I}

**Logic Diagram **

It can also be implemented with two half adders and one OR gate as shown below.

**Half Subtractor**

A half substractor is a combinational logic circuit that subtracts two bit and produces theri difference and borrow.

Difference (D) = AB + AB

Borrow (B) = AB

**Full Subtractor **

A full subtractor is a combinational logic circuit that performs subtraction involving three bit nemely minuend bit, subtrahend bit and borrow from the previous stage.

**Binary Adder**

A binary adder is digital circuit that produces the sum of two binary numbers. it can be constructed with full adders connected in cascade with output carry from each full adder connected to the input carry of next full adder in chain. An n bit adder requires n full adders.

**For example ** 4 bit adder can be made by using four full adder in cascade form.

The bits are adders with adders, starting from the least significant position (subscript0) to form the sum bit and carry bit.

**Binary Subtractor **

The subtractor of unsigned binary numbers can be done most conveniently by means of complements.

**Decimal Adder **

A decimal adder requires a minimum of nine inputs and five outputs. A variety of decimal adders are possible based on the code used to represent the decimal digits.

**BCD Adder**

A BCD Adder is a circuit that adds two BCD digits in parallel and produces a sum digit which is also BCD.

BCD number uses 10 symbols (0000 to 1001). A BCD adder circuit must be able to do the following :

- Add two, 4 bit BCD numbers using straight binary addition.
- if 4 bit sum is equal to or less than 9, the sum is a valid BCD number and no correction is needed.
- if the 4 bit sum is greater than 9 or if a carry is generated from the sum, the sum of invalid BCD number. then the digit 6 (0110) should be added to the sum to produce the valid BCD symbols.

**Code Converter **

A code converter is a circuit which accepts the input infomation in one binary code, converts it and produces an output in another binary code.

**Binary to BCD Converter**

This code converter combinational circuit is designed to convert binary to BCD code.

**BCD to Excess-3 Code**

Excess-3 code is modifide BCD code. the combinational circuit convert BCD code into excess-3 code.

In BCD to excess-3 truth table the unused codes are 1010, 1011, 1100, 1101, 1110 and 1111. so, place (don’t care) corresponding to these cells.

**Excess-3 Code to BCD Code Converter**

This circuit is designed to convert excess-3 code to BCD code.

unused code have x (don’t care condition).

**Decoders**

A decoders is a combinational logic circuit that converts binary information from n input lines to 2^{n} unique output lines.

The decoder presented are called n-to-m line decoders, where m < 2^{n}.

**Three to Eight Decoder**

In 3 to 8 decoder, the three inputs are decoded into eight outputs, each representing one of the minterms of the three input variable. 3 to 8 decoder is used for binary to octal conversion.

**Logic Diagram**

Decoders include one or more enable inputs to control the circuit operation. A two-to-four line decoder with an enable input constructed with NAND gates is shown below.

**Expanding Decoder**

Decoder with enable inputs can be connected together to form a larger size of decoder circuit.

Figure shows two, 3 to 8 line decoders with enable inputs connected to form a 4 to 16 line decoder.

**Example 1. **Implement the following functions using decoder and gates

F_{1}(A , B, C) = (0, 1, 3, 7)

F_{2} (A, B, C) = (2, 3, 7)

**Sol.** Given minterm is function of three variables so, 3 to 8 decoder is required to implement the above function. the OR gate is used for separste output because the given expression in form of sum of product.

**Encoder**

An encoder is a combinational circuit that converts information into coded form. it has 2^{n} (or fewer) input lines and n output lines.

**Example 2. ** Design an octal to binary code converter.

**Sol.** The octal to binary encoder has eight inputs and three outputs. in encoders it is assumed that only one input has a value of 1 at any given time.

**Multiplexer**

This is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. the selection of a particular input line is controlled by a set of selection lines. there are 2^{n} input lines and n selection lines whose bit combination determine which input is to be selected.

**4 x 1 Multiplexer**

In 4 x 1 multipexer 4 represents number of inputs and 1 represents output line. so two select lines are required to select one of the inputs.

**Logic symbol 4 to 1 Multiplexer**

The Boolean function of 4 to 1 multiplexer is written as follows :

Y = I_{0}S_{1}S_{0} + I_{1}S_{1}S_{0} + I_{2}S_{1}S_{0} + I_{3}S_{1}S_{0}

**Implementation of Boolean Expression Using MUX **

The boolean function may be implemented in 2^{n }to 1 multiplexer. the multiplexer inputs are n-1 variables, if we have a boolean function of n variables.

The multiplexer inputs are determined from the implementation table. this procedure can be explained by the following example :

**Example 3.** Implement the following boolean expression using 8 x 1 MUX.

F (A, B, C, D) = M (0, 2, 4, 6, 7, 9, 10)

**Sol. **Total number of variables = A, B, C, D = 4

Select line variable (2^{3}) = 3 (B, C, D)

Input variable 1 (A)

Now, we prepare the implementation table using the input variable and encircle the minterms 0, 2, 4, 6, 7, 9, 10 in the implementation table.

. if the two minterms in a column are encircled then 1 is placed to the corresponding multiplexer inputs.

. if the two minterms in a column are not encircled, the 0 is placed to the corresponding multiplex input.

. if the minetrms in fist row or second row is encircled (only one row is encircled not other) then apply the encircle row of variable to the corresponding multiplexer inputs.

Thus, the logic diagram of given boolean expression

**Example 4. **Implement the following boolean function

F (A, B, C, D) = (0, 1, 4, 6, 7, 9, 11, 15)

Using

(a) 8 X 1 MUX

(b) 4 X 1 MUX

(c) 2 X 1 MUX

**Sol.** (a) 8 X 1 MUX

F (A, B, C, D) = (0, 1, 4, 6, 7, 9, 11, 15)

Total number of variables = 4 (A, B, C, D)

Select line = 3(B, C, D)

Input = 1 (A)

(b) Using 4 x 1 MUX

Total number of variables = 4 (A, B, C, D)

Select line = 2 (C, D)

Input = 2 (A,B)

Implementation table

I_{0} = A B + AB = A (B + B) = A

I_{1} = A B + AB = B (A + A) = B

I_{2} = AB

I_{3} = AB + AB + AB

= AB + A (B + B) = AB + A

(c) 2 x 1 MUX

total number of variables = 4 (A, B, C, D)

Select line = 1 (D)

Inputs = 3 (A, B, C)

I_{0} = A B C + ABC + ABC

= AC (B + B) + ABC

= AC + ABC

I_{1} = A B C + ABC + ABC + ABC + ABC

= (A + A) BC + ABC + ABC + ABC

= BC + ABC + AC (B + B)

= BC + ABC + AC

**Example 5. **Implement the following boolean function with 8 : 1 multiplexer.

F (A, B, C, D) = IIM (0, 1, 3, 5, 8, 12, 15)

**Sol. **firstly convert the given maxterm into minterms :

F (A, B, C, D) = M (2, 4, 6, 7, 9, 10 ,11, 13, 14)

Total number of variable = 4 (A, B, C, D)

Number of inputs = 1 (A)

Selsct lines = 3 (B, C, D)

Implementation table

**Example 6. **Implement the following boolean function with 8 : 1 multiplexer.

F (A, B, C, D) = M (0, 2, 3, 4, 7, 8, 15) + d (1, 5, 6, 10, 11)

**Sol. **Total number of variables = 4 (A, B, C, D)

Select line = 3 (B, C, D)

Input line = 1 (A)

**Demultiplexer**

A decoder with an enable input can function as a demultiplexer. A demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2^{n} possible output lines.

**1 to 4 Demultiplexer**

in 1 to 4 demultiplexer 1 represents demultiplexer input and 4 represents the number of output lines. thus, 2 (2^{2} = 4) select lines is required to construct 1 to 4 demultiplexer.

**Example 7. ** Implement the full adder by using 1 to 8 demultiplexer.

in terms of minterms it can be represented as

Sum = m (1, 2, 4, 7)

Carry = m (3, 5, 6, 7)

The implementation of full adder using demultiplexer shown below :

**Parity Generator **

A parity generator is combinational logic circuit that generates the parity bits. A parity bit is an extra bit which is added in binary message such that the total number of 1 s in the message can be either even of odd according to the parity used. there are two types of parity generators and checkers :

**Even Parity Generator**

An even parit generator is a combinational circuit that genertes a word which always contain even number of 1’s. let us consider an example of 4 bit information with even parity.

K-map for P with inputs A, B, C and D

P = n (1, 2, 4, 7, 8, 11, 13, 14)

P = A * B * C * D

**Odd parity generator**

Odd parity generator is a combinational circuit that generates a word which always contain odd number of 1’s let us consider an example of 4 bit information with odd parity

**Parity Checker**

At the receiving end a combinational logic circuit is used to check the parity of the received information. the combinational logic circuit used at the receiver to check the parity of received inforamtion is known as the parity checker. there are two types of parity checker

- Even parity checker
- Odd parity checker
**Even parity checker**

Even parity checker is a combinational logic circuit which checks the parity of inputs and provides the output of 1. for an even parity checker, if the parity of input message is even, then the output is zero. otherwise the output is 1.

After solving k-map for PE, we get

PE = A * B * C * D * P

**Magnitude Comparators **

The basic function of a magnitude comparator is to compare the magnitudes of two quantities in order to determine the relationship to those quantities. A comparator circuit determines whether two number are equal.

**1 bit Magnitude Comparator **

One bit compartor is combinational logic circuit which compares the two binary inputs and gives output.

From the truth table

(A > B) = AB

(A = B) = AB + AB = A . B

(A > B) = AB

**2-bit Comparator **

It is a combinational logic circuit used to compare 2 bit from each input.

(A > B) = A_{0}B_{1} B_{0} + A_{1}B_{1} + A_{1} A_{0} B_{0}

(A = B) = (A_{0} B_{0}) (A_{1} B_{1})

(A > B) = A_{1} A_{0} B_{0} + A_{0} B_{1} B_{0} + A_{1}B_{1}

**Programmable Logic Devices **

A programmable logic devices is an IC that is user configurable and is capable of implementing logic fucntions. it is an LSI chip. PLDs can reprogrammed in a few second and hence, give more flexibility to experiment with designs.

**Read Only Memory (ROM)**

A read only memory (ROM) is a memory device in which permanent binary information is stored. the binary information is specified by the designer and then embedded in the unit to form the required interconnection pattern. once the pattern is established, it stays within the unit when the power is turned off and on again. it is used only for reading the information from it.

A ROM which can be programmed is called a PROM. the process of entering information in a ROM is known as programming. ROMs are used to store information which is of fixed type.

ROMs can be used for designing combinational logic circuits. depending on the type of ROM used, a user can design and modify the circuits easily.

**ROM Organization**

A biock diagram of a ROM is shown in figure. it consists of k inputs and n outputs. the inputs provide the address from the memory and the outputs give the data bits of the stored word which is selected by the address. integrated circuit ROM chips have one or more enable inputs and sometimes come with three state outputs to facilitate the construction of large arrays of ROM.

Figure shows the internal logic construction of the ROM. The five inputs are decoded into 32 distinct outputs by means of a 5 x 32 decoder. ROM is basically a decoder with k inputs and 2^{k} output lines followed by a bank of OR gates. each output of the decoder represents a memory address.the 32 output of the decoder are connected to each of the 8 OR gates.

Each OR gate has 32 input connections and there are 8 OR gates, the ROM contains 32 x 8 = 256 internal connections. in general, a 2^{k} x n ROM will have an internal k x 2^{k} decoder and n OR gates. each OR gate has 2^{k} inputs which are connected to each of the outputs of the decoder.

The programmable intersection between two lines is sometimes called a cross point.

**Example 8. **Design a combinational circuit using a ROM. the circuit accepts a 3 bit number and generates an output binary number equal to the square of the input number.

**Sol.** The first in the desing is to derive the truth table of the combinational circuit. in most cases this is all that is needed. in other cases, we can use a partial truth table for the ROM by utillzing certain properties in the output variables.

The minimum size ROM needed must have three inputs and four outputs. three inputs specify eight words, so the ROM must be size 8 x 4. the ROM implementation is shown in figure. the three input specify eight words of 4 bit eac. the ROM truth table in fig. (a) specifies the information needed for programming the ROM. The block diagram of fig. (b) shows the required connections of the combinational circuit.

B_{5} = M (6, 7)

B_{4} = M (4, 5, 7)

B_{3 } = M (3, 5)

B_{2} = M (2, 6)

B_{1} = 0

B_{0} = M (1, 3, 5, 7) = A_{0}

**Types of ROMS**

There are two types of semiconductor technologies used for the manufacturing of ROM ICs. first one is bipolar technology and another is MOS devices respectively. the process of entering information into a ROM is called programming the ROM. bipolar ROMs and MOS ROMs use different techniques of programming. depending upon the programming process used, the ROMs are categorized as follows

**Mask programmable read only memory (MROM)** In this type of read only memory (ROM), the user specifies the data to be stored to the manufacturer of the memory. the data pattern specified by the user are programmed as a part of the fabrication process. once programmed, the data pattern cannot be changed. this type of read only memory is referred to as ROM.

**Erasable programmable Read only memory (EPROM) **In this type of memory, data can be written any number of times means they are reprogrammable. before it is reprogrammed, the contents already stored are erased by exposing the chip to ultraviolet radiation for about 30 minute. this type of memory is referred to as EPROM. EPROMs are possible only in MOS technology. programming is done using a PROM programmer.

**Electrically Erasable and programmable read only memory (EEROM or E ^{2} PROM) **This is another type of reprogrammable memory in which erasing is done electrically rather than exposing the chip to the ultraviolet radiation. it is referred to as EEPROM or electrically alterable ROM (EAROM).

**Combinational progra-mmable logic Devices**

A combinational PLD is an integrated circuit with programmable gates divided into an AND array and an OR array to provide an AND-OR sum of qproducts implementation. there are three major types of combinational PLDs and they differ in the placement of the programmable connection in the AND-OR array. the various PLDs used are PALs (programmable array logics), PLAs (programmable logic arrays) and PROMs (programmable read only memories).

The most flexible PLD is the programmable logic array (PLA) where both the AND and OR arrays can be programmed.