what is differentiate between unipolar and bipolar logic families ? definition meaning characteristics of logic families pdf , classification and comparison ?

**Logic Families**

**Logic families ** The set of compatible ICs with the same logic levels and same supply voltages fabricated to perform the various logic functions is known as logic family.

**Logic Families**

Based on the fabrication technology, logic families are classified into two types

. bipolar logic family

. unipolar logic family

**Unipolar logic family**

In unipolar logic families, unipolar devices are the ked elements. the examples of unipolar families include PMOS, NMOS and CMOS.

**Bipolar logic family**

in bipolar logic families, transistors and diodes are used as ked elements. on the basis of operations of transistors in ICs. bipolar logic families are further classified as

. saturated bipolar logic families

. unsaturated bipolar logic families

in saturated bipolar logic families, transistors work in saturation region. thus the speed of saturated bipolar logic family is low. examples of saturated bipolar logic families are

. resistor – transistor logic

. direct coupled transistors logic

. integrated injection logic

. diode-transistor logic

. high-threshold logic

. transistor -transistor logic

in non-saturated bipolar logic families, rate transistors operate in active region. the speed of non-saturated bipolar logic families is high as compared to saturated logic families. example of unsaturated bipolar logic families are

. schottky transistor -transistor logic

. emitter – coupled logic

the transistor is one of the key elements used in logic families. one of the important applications of the transistor is the switch.

**Transistor as a Switch**

Transistor is one of the basic elements of logic families. it operates as a switch. in switching circuits, transistors operate in cut-off or saturation region. the cut-off condition is referred to as switch-off and saturation is referred to as switch-on.

in the cut-off region, both emitter and collector junctions are in reverse bias condition and only reverse current flows in the transistor which is negligible.

in the saturation region, both emitter and collector junctions are in forward bias condition.

The circuit of a transistor working as a switch is shown in figure.

in the cut-off region, collector current I_{C} = 0

V_{OUT} = V_{CC}

When the transistor is operating in cut-off, the output is equal to V_{CC} and it is referred to as high (logic 1).

in the saturation region

V_{OUT} = V_{CE}

When the transistor is operating in saturation, the ouput is equal to V_{CE(SAT)} and it is referred to as low (logic 0).

**Characteristics of Digital ICs**

The selection of a logic family for a particular application is based on its characteristics. following are the parameters used to compare the performance of digital ICs :

- speed of operation
- power dissipation
- figure of merit
- curent to voltage parameters
- noise immunity
- fan-out
- fan-in
- power supply requirements
- operating temperature

**Speed of Operation**

Speed of operation is specified in terms of propagtion delay time. it is the average of propagation delay time from high to low state and low to high state.

The delay times are measured between 50% voltage levels of input and output waveforms.

t_{p} = t_{phl} + t_{plh}/2

Where,

t_{PHL}. = The delay time measured, when output changes from high to low state.

t_{PLH} = The delay time measured, when output changes from low to high state.

**Power Dissiption**

In electronic circuits, every circuit requires a certain amount of electric power for its operation whenever an extermal source is connected to the electronic circuits, some power is dissipated in electronic circuits. power dissipation should be as minimum as possible. it is the product of input voltage and input current.

**Example 1.** A digital gete has an input voltage V_{CC} equal to 5 V. The input current is 2 mA for high output and 3.4 mA for fow output. find the power dissipated for 50% duty cycle.

**Sol. ** Average value of input current

= 2 + 3.4 / 2 = 2.7 mA

power dissipation = 5 x 2.7 = 13.5 mW

**Figure of Merit**

Figure of merit is a product of propagation delay and power dissipation. it is measured in terms of pico-joules (ms x mW = pJ).

**Current and Voltage Parameters**

Current and voltage parameters define the minimum and maximum limit of current and voltage for input and output of a logic family.

**V _{IH} (High level input voltage) **it is the minimum input voltage corresponding to logic 1 state.

**V**it is the maximum input voltage corresponding to logic 0 state.

_{IL}(Low level input voltage)**V**it is the minimum output voltage corresponding to logic 1 state.

_{OH}(High level output voltage)**V**it is the maximum output voltage corresponding to logic 0 state.

_{OL}(Low level output voltage)**I**it is the minimum input curent corresponding to logic 1 state.

_{IH}(High level input voltage)**I**it is the maximum input current corresponding to logic 0 state.

_{IL}(Low level input current)**I**it is the minimum input current corresponding to logic 0 state. this current is also referred to as source current.

_{OH}(High level output current)**I**it is the maximum output current corresponding to logic 0 state. it is also referred to as the sink current.

_{ol}(Low level output current)**Noise Immunity**

The noise immunity of digital circuit is defined as the ability of a circuit to tolerate the noise signals. A quantitativae measure of noise immunity is known as noise margin. logic 1 state noise margin and logic 0 state noise marrgin can be calculated as

Logic 1 state noise margin

I = V

_{OH}– V

_{IH}

Logic 0 state noise margin

0 = V

_{IL}– V

_{OL}

It is important that for logic familise

V

_{OH}> V

_{IH}and V

_{IL}> V

_{OL}

**Example 2.**A NOT gate has V

_{IL}= 0.8 V, V

_{IH}= 2.5 V, V

_{OH}= 0.4 V, V

_{OH}= 3.6 V. If two such gates are cascaded, find the low and high noise margins.

**Sol.**high noise margin

I = V

_{OH}– V

_{IH}

= 3.6 – 2.5 = 1.1 V

Low noise margin

0 = V

_{IL}– V

_{OL}

= 0.8 – 0.4 = 0.4 V

**Fan-out**

fan-out is the capability of a logic gate to drive the maximum number of similar gates. fan-out of a logic family can be calculated as

fan-out = minimum of {I

_{OH}/I

_{IH}, I

_{OL}/I

_{IL}}

**Fan-in**

it is the maximum number of inputs which the logic circuit can handle.

**Power Supply Requirements**

Every electronic circuit requires supply voltage to operate. this refers to the maximum value of the input voltage and the amount of power required.

**Operating Temperature**

The operating temperature is defined as the range of temperature in which as IC functioning properly. for commercial and industrial applications, the temperature limits of digital ICs are 0

^{0}C to 70

^{0}C and for militancy applications the range is – 55

^{0}C to 125

^{0}C.

**Resistor – Transistor Logic**

As the name indicates this family uses resistors and transistors. in RTL, transistor operate in cut-off region or saturation region according to the input applied.

Figure shown circuit of a two-inputs resistor-transistor logic NOR gate. here, A and B are the inputs of the gate and Y is the output.

in terms of 0 and 1, the above table can be written as in table (b).

The RTL suffers from a few drawbacks as listed below.

- low noise margin (typically 0.1 v).
- fan-out is poor (typically 5)
- propagation delay is high and the speed of operation is low (typically 12 ns).
- high power dissipation (typiacally 12 mW).

**Direct Coupled Transistor logic Circuit (DCTL)**

In direct coupled transistors logic input is directly coupled to the transistor base. in DCTL, the transistor operates in saturation or cut-off region.

The DCTL, circuit works in similar manner as RTL. it is not popular because of current hogging.

**Diode Transistor Logic**

This logic uses diodes and transistors. the figure shows the circuit of low inputs diode transistor logic NAND gate.

In DTL, the transistors operates in saturation and cut-off regions.

the operation of the circuit is summarized in table (a).

in terms of 0 and 1, table (a) can be written as in table (b).

These are the advantages and disadvantages of DTL over RTL.

**Advantages**

- fan-out is high.
- power dissipation is 8-12 mW.
- noise immunity is good

**Disadvantages**

- more elements are required.
- propagation delay is more (typically 30 ns) and hence,the speed of operation is less.

**Modified Diode-Transistor logic**

Generally, more fan-out gates are preferred for most of the applications. the fan-out of a logic gate is increased by increasing the current supply of the gate (source current).

Replacement of diode D_{3} by the transistor T_{1} increases the base current of the transistor and the circuit is referred as a modiffed diode-transistor logic . the modified diode-transistor logic has more fan-out as compared to DTL. the circuit diagram of a modified diode-transistor logic is shown in figure.

**Transistor – Transistor Logic (TTL)**

Transistor -transistor logic is one of the generally used saturated logic families. transistor is the basic element of this logic family and can operates either in out-off or saturated region. the first version of TTL is named as the standard TTL.

Standard TTLs are available in various forms

- TTL with passive pull-up
- TTL with totem-pole output
- TTL with open collector output
- Tristate TTL.

**TTL with Passive Pull-up**

Figure shows a two-input TTL NAND gate with passive pull-up. transistor t_{1} has two emitter terminals. these terminals work as the inputs of the gate i.e., input A and input B. the input voltages are logic 0 or logic 1, where logic 0 corresponds to 0.2 V and logic 1 corresponds to +5 V.

The operation of the circuit is summarized in table (a).

In terms of 0 and 1, table (a) can be written as follows:

**Passive Pull-up**

When both inputs are high, the transistor T_{3} operates in saturation region V_{O} = V_{CE} _{SAT} and the capacitor of loaded gate is charged up to V_{CE, SAT}. When one or more than one inputs change to logic 0, the corresponding emitter junction or junctions of T_{1} are forward biased and T_{3} goes into cut-off. the capacitor of the loaded gate starts charging towards V_{CC} through the resistor R_{C3} as shown in figure.

the capacitor of the loaded gate is pulled towards V_{CC} through the passive component R_{C3} and hence, the circuit is known as TTL with passive pull-up.

in TTL with passive pull-up, the time constant is R_{C3} x C_{0.}