transconductance amplifier formula | operational transconductance amplifier applications

operational transconductance amplifier applications , transconductance amplifier formula class 12th ideal characteristics.
Transconductance
The transconductance of a FET is defined as
g_m = I_D/V_GS /v_{ds = 0}  uA/V
Because the changes in I_D and V_GS are equivalent to AC current and voltage. this equation can be written as
The unit of g_m is mho or siemens.
Typical value of g_m is 2000 mA/V.
The value of g_m can be obtained from the transconductance curve as shown in fig. 9(a).
If A and B points are considered, then a change in V_GS Produces a change in I_D. The ratio of I_D and V_GS is the value of g_m between A and B points. if C and D points are conidered, then same change in V_gs produces more change in I_d. therefore, g_m value is higher. in a natshell, g_m tells us how much control gate voltage has over drain current. higher the value of g_m the more effective is gate voltage in conrtroling gate current. the second parameter R_D is the drain resistance.
R_D = V_DS / I_D /_{VGS = 0}                                  (R_D is negligible)
Similar to bipolar junction transistor, JFET can also be used as an amplifier. the AC equivalent circuit of a JFET is shown in fig 9(b).
The resistance between the gate and the source R_GS is very high. the drain of a JFET acts like a current source with a value of g_m V_GS. This mocel is applicable at low frequencies.
From the AC equivalent model,
I_D = g_mV_GS + V_DS/R_D
When                     I_D = 0, V_DS/V_GS = – g_mR_D
The amplification factor u for FET is defined as
u = V_DS/V_GS /I_{D = 0}                   (u = g_mR_D)
When V_GS = 0, g_m has its maximum value. the maximum value is designated as g_mo . again consider the equation
I_D = I_DSS [1 – V_GS /V_GS(OFF) }²
g_m = I_D / V_GS = 21_DSS  [1 – V_GS/V_GS(OFF)] [-1 / V_GS(OFF)
g_m = -2I_DSS/V_GS(OFF) [1 – V_GS/V_GS(OFF)]
when V_GS = 0, g_m = g_mo = -2I_DSS /V_GS(OFF)
g_m = g_mo [1 – V_GS / V_GS(OFF)]
As V_GS increases, g_m decreases linearly.
V_GS(OFF) = -2I_DSS / g_m
Measuring I_DSS and g_m, V_GS(OFF) can be determined.
FET as Amplifier
Fig 10(a) shows a common source amplifire.
When a small AC signal is coupled into the gate it produces variations in gate-source voltage. this produces a sinusoidal drain current. since, an AC current flows through the drain resistor. An amplified AC voltage is obtained more drain current, which means that the drain voltage is decreasing. since, the positive half cycle of input voltage produces the negative half cycle of output voltage, we get phase inversion in a CS amplifier.
The AC equivalent circuit is shown in fig. 10(b).
The AC output voltage is
V_OUT = – g_mV_GSR_D
Negative sign means phase inversion. because the AC source is directly connected between the gate source terminals therefore AC input voltage equals
V_In = V_GS
The voltage gain is given by
A_V = V_OUT / V_In = – g_mR_D
A_V = Unloaded voltage gain
The further simplified model of the amplifiers shown in fig. 11(c).
Z_in is the input impedance. At low frequencies, there is parallel combination of R₁||R₂||R_GS. since, R_GS is very large, it is parallel combination of R₁ and R₂. V_in is output voltage and R_D is the output impedance.
Because of non-linear transconductance curve, a JFET distorts large signals, as shown in fig. 11(d).
Given a sinusoidal input voltage, we get a non-sinusoidal output current in which positive half cycle is elongated and negative cycle is compressed. this type of distortion is called square law distortion because the transconductance curve is parabolic.
This distortion is undesirable for an amplifier. one way to minimize this is to keep the smill signal. in that case a part of the curve is used and operation is approximately linear. some times swamping resistor is used to minimize distortion and gain constant. now, the source is no longer AC  grond as shown in fig. 11(e).
The drain current through r_s produdes an AC voltage. between the source and ground. if r_s is large enough the local feedback can swamp out the non-linearity of the curve. then the voltage gain approaches an ideal value of R_D/r_s.
Since, R_GS approaches infinity therefore, all the drain current flows through r_s producing a voltage drop of g_mV_GSr_s. the AC equivalent circuit is shown in fig. 11(f).
V_GS + g_mV_GS‘r_s – V_in = 0
V_in = (1 + g_mr_s) V_GS
V_OUT = – g_mR_DV_GS
A = -g_mR_D / 1 + g_mr_s = -R_D / r_s + 1/g_m
The voltage gain reduces but voltage gain is less effective by change in g_m‘r_s must be greater than 1/g_m only then,
V_GS = – R_D / r_s
Example 1. Determine g_m for an n-channal JFET with characteristic curve shown in figure below.
sol.  we select an operating region which is approximately in the middle of the curves; that is, between V_GS  = – 0.8 V and V_DS = – 1.2 V, I_D = 8.5 mA and I_D = 5.5 mA. Therefore, the teansconductance of the JFET is given by
g_m = i_d / v_gs /v_{gs = constant}          = 7.5 mho
Design of JFET Amplifier
To design a JFET amplifier, the Q point for the DC bias current can be determined graphically. the DC bias current at the Q point should lie between 30% and 70% of I_DSS. This locates the Q point in the linear region of the characteristic curves.
 
The relationship between I_D and V_GS can be plotted on a dimensionless graph (i.e.,a normalized curve) as shown in fig 12.
The vertical axis of this graph is I_D / I_DSS and the horizontal axis is V_GS /V_P. The slope of the curve is g_m.
A reasonable procedure for locating the quiescent point near the centre of the linear operating region is to select I_DO ~ I_DSS / 2 and V_{GS, Q} ~ 0.3 V_P. Note that this is near the midpoint of the curye. next we select V_DS ~ V_DD /2 this gives a wide range of values for V_DS that keep the transistor in the pinch-off mode.
The transconductance at Q point can be found from the slope of the curve of fig. 12 and is given by
g_m = 1.41 I_DSS / V_P
Example 2. Determine g_m for a JFET, where I_DSS = 7 mA, V_P = – 3.5 V and V_DD = 15 V. Choose a reasonable location for the Q point.
Sol. Lat us select the Q point as give below
I_DQ = I_DSS/2  = 3.5 mA
V_{DS Q} = V_DD/2   = 7.5 V
V_{GS, Q} = 0.3V_P = – 1.05 V
The transconductance g_m is found from the slope of the curve at the point I_D/I_DSS = 0.5 and V_GS /V_P = 0.3 Hence,
g_m = 1.41 I_DSS/V_P = 2840 umho
JFET as Analog Switch
JFET can be used as an analog switch as shown in fig. 13(a). it is the major application of JFET. the idea is to use two points on the load line, cut-off and saturation when JFET is cut-off, it is like an open switch. when it is saturated, it is like a closed switch.
When V_GS = 0, the JFET is saturated and operates at the upper end of the load line. when V_GS is equal to or more negative than V_GS(Off), it is cut-off and operates at lower end of the load line (open and closed switch). this is shown in fig. 13(b).
Only these two points are used for operetion when used as a switch. the JFET is normally saturated well below the knee of the drain curve. for this reason the drain current is much smaller than I_DSS.
FET as a Shunt Switch
FET can be used as a shunt switch as shown in fig. 14. when V_con = 0, the JFT is saturated and the switch is closed. when V_con is more negative FET is like an open switch. the equivalent circuit is also shown in fig. 14.
FET as a Series Switch
JFET can also be used as series switch as shown in fig. 15. when control is zero, the FET is a closed switch. when V_con = negative, the FET is an open switch. it is better than shunt switch.
Multiplexing
One of the important application of FET is in analog multiplexer. analog multiplexer is a circuit that selects one of the output lines as shown in fig. 16. when control voltages are more negative, all switches are open and output is zero. when any control voltage becomes zero the input is transmitted to the output.
Intro Exercise – 3

1. In the circuit shown below the parameters are g_m = 1 mA /V, r_o = 50 k. the gain A_V = V_O / V_S is

(a) – 8.01
(b) 8.01
(c) 14.16
(d) -14.16

2. In the given circuit of figure, if V_TH = 0.4 V, the transistor M₁ is operating in

(a) linear region
(b) satruation region
(c) M₁ is off
(d) cannot be cletermined

3. while biasing JFET, if drain and source are interchanged, then

(a) device will work normally
(b) device will get damaged
(c) device will work but value of I_D will get affected
(d) device will not operate at all

4. the values of V_C and V_GS for the circuit shown in figure are

(a) -2 V, -2 V
(b) 2 V, 2 V
(c) 2 V, -2 V
(d) -2 V, 2 V

5. A three stage cascaded amplifier of identical non-interacting FET common source stage has all over an voltage gain of |1000| and overall bandwidth of 25×10⁶ rad/s.

Given g_m = 5 mA /V, the shunt capacitance of each stage is given by
(a) 1.6 pF
(b) 10 pF
(c) 20 pF
(d) 3.2 pF

6. Given, for an FET, g_m = 95 mA/V total capacitance is 500 pF. for a voltage gain of – 30, the bandwidth will be

(a) 19 MHz
(b) 6.3 MHz
(c) 100 MHz
(d) 3 MHz

7. in the circuit of figure the transistor parameters are as follows:

V_tp = – 2 V, K_P = 1mA/V² , V_SG =?
(a) -3.77 V
(b) 4.37 V
(c) -1.77 V
(d) 1.77 V

8. The p-MOS transistor in figure has parameters

V_TP = – 1.2 V, w/L  = 20
and         K_P = 30 uA/V²
If I_D = 1 mA and V_D = – 5 V, then values of R_S and R_D are
(a) 4 k, 5.8 k
(b) 4 k, 5k
(c) 5.8 k, 4 k
(d) 6.98 k, 5 k
Statements for linked answer questions 9 and 10
For the circuit shown below transistor parameters are V_TN = 2 V, K_n = 0.5 mA/V² and  = 0. the transistor is in saturation.

9. if I_DQ is to be 0.4 mA, the value of V_GS,Q is

(a) 5.14 V
(b) 4.36 V
(c) 2.89 V
(d) 1.83 V

10. The value of g_m and r_o are

(a) 0.89 mS, infinite
(b) 0.89 mS, zero
(c) 1.48 mS, zero
(d) 1.48 mS, infinite
Answers with Solutions

1. (a) The small signal equivalent circuit ia as shown below.

V_GS = 50 /50+2 v_s
V_a = g_mV_GS (50||10) = -50/52 V_S (8.33)
A_V = V_O / V_S = – 8.01

2. (b) For p-channel MOSFET.

V_{SD (Sat)} = V_SG + V_TH = (1 – 0) – 0.4 = 0.6
V_SD = V_S – V_D = 1 – 0.3 = 0.7
Here,   V_SD > V_{SD (Sat)}
So, M₁ is in saturation region.

3. (a) The reversibility of terminals is unique in the case of JFET.
4. (a) V_{GS, Q} = – V_GG = – 2 V

V_GS = V_G – V_S = – 2 V

5. (b) Gain /stage = 1000 = 10

BW/ stage = 2 x 25 x 10⁶
C = g_m / G (BW)
= 5 x 10^-3 / 10 x 50 x 10⁶ = 10 pF

6. (b) g_m / c = A_v x BW

or                  95 x 10^-3 / 500 x 10^-12 = 30 x BW
or              BW = 6.3 MHz

7. (b) R₁ = 10 K, R₂ = 20 K, R₂ = 1 K, R_D = 3 K,

V_G = [R₂ / R₁ + R₂] (30) – 15
= (20 / 10 + 20) (30) – 15
= 5 V
Assume transistor is in saturation.
I_D = 15 – V_S / R_S = K_P (V_SG + V_TP)²
15 – V_S = R_S K_P (V_SG + V_TP)²
where               V_S = V_G + V_SG
15 – (V_G + V_SG) = (1 x 10³) (1 x 10^-3) (V_SG + V_TP)²
15 – 5 – v_sg = (V_SG + V_TP)²
10 –  V_SG = (V_SG + V_TP)²
10 – V_SG = (V_SG)² + 2V_SG – V_TP + (V_TP)²
10 – V_SG = (V_SG)² – 4V_SG + 4
(V_SG)² – 3V_SG – 6 = 0
V_SG = 4.37 V, – 1.37 V

8. (d) K_P = (30 x 10^-6 / 2) (20) = 0.3 mA/V²

K_P = (K_P /2 . w/L)
I_D = K_P (V_SG + V_TP)²
1 = 0.3 (V_SG – 1.2)²
V_SG = 3.02 V, V_G = 0
V_S = V_SG = 3.02 V
I_D = 10 – V_S / R_S
R_S = 10 – 3.02 / 1 = 6.98 K
I_D = V_D – (-10) / R_D
R_D = – 5 + 10 / 1 = 5 K

9. (c) I_DQ = K_N (V_GS – V_TN)²

0.4 = 0.5 (V_GS – 2)²
V_GD = 2.89 V

10. (a) g_m = 2k_n (V_GS – V_TN) = 2 (0.5) (2.89 – 2)

= 0.89 mA/V = 0.89 mS
r_o = (I_DQ)^-1, = 0    r_o = ₀₀