# transconductance amplifier formula | operational transconductance amplifier applications

By   July 8, 2020

operational transconductance amplifier applications , transconductance amplifier formula class 12th ideal characteristics.
Transconductance
The transconductance of a FET is defined as
gm = ID/VGS /vds = 0  uA/V
Because the changes in ID and VGS are equivalent to AC current and voltage. this equation can be written as
The unit of gm is mho or siemens.
Typical value of gm is 2000 mA/V.
The value of gm can be obtained from the transconductance curve as shown in fig. 9(a).
If A and B points are considered, then a change in VGS Produces a change in ID. The ratio of ID and VGS is the value of gm between A and B points. if C and D points are conidered, then same change in Vgs produces more change in Id. therefore, gm value is higher. in a natshell, gm tells us how much control gate voltage has over drain current. higher the value of gm the more effective is gate voltage in conrtroling gate current. the second parameter RD is the drain resistance.
RD = VDS / ID /VGS = 0                                  (RD is negligible)
Similar to bipolar junction transistor, JFET can also be used as an amplifier. the AC equivalent circuit of a JFET is shown in fig 9(b).
The resistance between the gate and the source RGS is very high. the drain of a JFET acts like a current source with a value of gm VGS. This mocel is applicable at low frequencies.
From the AC equivalent model,
ID = gmVGS + VDS/RD
When                     ID = 0, VDS/VGS = – gmRD
The amplification factor u for FET is defined as
u = VDS/VGS /ID = 0                   (u = gmRD)
When VGS = 0, gm has its maximum value. the maximum value is designated as gmo . again consider the equation
ID = IDSS [1 – VGS /VGS(OFF) }2
gm = ID / VGS = 21DSS  [1 – VGS/VGS(OFF)] [-1 / VGS(OFF)
gm = -2IDSS/VGS(OFF) [1 – VGS/VGS(OFF)]
when VGS = 0, gm = gmo = -2IDSS /VGS(OFF)
gm = gmo [1 – VGS / VGS(OFF)]
As VGS increases, gm decreases linearly.
VGS(OFF) = -2IDSS / gm
Measuring IDSS and gm, VGS(OFF) can be determined.
FET as Amplifier
Fig 10(a) shows a common source amplifire.
When a small AC signal is coupled into the gate it produces variations in gate-source voltage. this produces a sinusoidal drain current. since, an AC current flows through the drain resistor. An amplified AC voltage is obtained more drain current, which means that the drain voltage is decreasing. since, the positive half cycle of input voltage produces the negative half cycle of output voltage, we get phase inversion in a CS amplifier.
The AC equivalent circuit is shown in fig. 10(b).
The AC output voltage is
VOUT = – gmVGSRD
Negative sign means phase inversion. because the AC source is directly connected between the gate source terminals therefore AC input voltage equals
VIn = VGS
The voltage gain is given by
AV = VOUT / VIn = – gmRD
The further simplified model of the amplifiers shown in fig. 11(c).
Zin is the input impedance. At low frequencies, there is parallel combination of R1||R2||RGS. since, RGS is very large, it is parallel combination of R1 and R2. Vin is output voltage and RD is the output impedance.
Because of non-linear transconductance curve, a JFET distorts large signals, as shown in fig. 11(d).
Given a sinusoidal input voltage, we get a non-sinusoidal output current in which positive half cycle is elongated and negative cycle is compressed. this type of distortion is called square law distortion because the transconductance curve is parabolic.
This distortion is undesirable for an amplifier. one way to minimize this is to keep the smill signal. in that case a part of the curve is used and operation is approximately linear. some times swamping resistor is used to minimize distortion and gain constant. now, the source is no longer AC  grond as shown in fig. 11(e).
The drain current through rs produdes an AC voltage. between the source and ground. if rs is large enough the local feedback can swamp out the non-linearity of the curve. then the voltage gain approaches an ideal value of RD/rs.
Since, RGS approaches infinity therefore, all the drain current flows through rs producing a voltage drop of gmVGSrs. the AC equivalent circuit is shown in fig. 11(f).
VGS + gmVGS‘rs – Vin = 0
Vin = (1 + gmrs) VGS
VOUT = – gmRDVGS
A = -gmRD / 1 + gmrs = -RD / rs + 1/gm
The voltage gain reduces but voltage gain is less effective by change in gm‘rs must be greater than 1/gm only then,
VGS = – RD / rs
Example 1. Determine gm for an n-channal JFET with characteristic curve shown in figure below.
sol.  we select an operating region which is approximately in the middle of the curves; that is, between VGS  = – 0.8 V and VDS = – 1.2 V, ID = 8.5 mA and ID = 5.5 mA. Therefore, the teansconductance of the JFET is given by
gm = id / vgs /vgs = constant          = 7.5 mho
Design of JFET Amplifier
To design a JFET amplifier, the Q point for the DC bias current can be determined graphically. the DC bias current at the Q point should lie between 30% and 70% of IDSS. This locates the Q point in the linear region of the characteristic curves.

The relationship between ID and VGS can be plotted on a dimensionless graph (i.e.,a normalized curve) as shown in fig 12.
The vertical axis of this graph is ID / IDSS and the horizontal axis is VGS /VP. The slope of the curve is gm.
A reasonable procedure for locating the quiescent point near the centre of the linear operating region is to select IDO ~ IDSS / 2 and VGS, Q ~ 0.3 VP. Note that this is near the midpoint of the curye. next we select VDS ~ VDD /2 this gives a wide range of values for VDS that keep the transistor in the pinch-off mode.
The transconductance at Q point can be found from the slope of the curve of fig. 12 and is given by
gm = 1.41 IDSS / VP
Example 2. Determine gm for a JFET, where IDSS = 7 mA, VP = – 3.5 V and VDD = 15 V. Choose a reasonable location for the Q point.
Sol. Lat us select the Q point as give below
IDQ = IDSS/2  = 3.5 mA
VDS Q = VDD/2   = 7.5 V
VGS, Q = 0.3VP = – 1.05 V
The transconductance gm is found from the slope of the curve at the point ID/IDSS = 0.5 and VGS /VP = 0.3 Hence,
gm = 1.41 IDSS/VP = 2840 umho
JFET as Analog Switch
JFET can be used as an analog switch as shown in fig. 13(a). it is the major application of JFET. the idea is to use two points on the load line, cut-off and saturation when JFET is cut-off, it is like an open switch. when it is saturated, it is like a closed switch.
When VGS = 0, the JFET is saturated and operates at the upper end of the load line. when VGS is equal to or more negative than VGS(Off), it is cut-off and operates at lower end of the load line (open and closed switch). this is shown in fig. 13(b).
Only these two points are used for operetion when used as a switch. the JFET is normally saturated well below the knee of the drain curve. for this reason the drain current is much smaller than IDSS.
FET as a Shunt Switch
FET can be used as a shunt switch as shown in fig. 14. when Vcon = 0, the JFT is saturated and the switch is closed. when Vcon is more negative FET is like an open switch. the equivalent circuit is also shown in fig. 14.
FET as a Series Switch
JFET can also be used as series switch as shown in fig. 15. when control is zero, the FET is a closed switch. when Vcon = negative, the FET is an open switch. it is better than shunt switch.
Multiplexing
One of the important application of FET is in analog multiplexer. analog multiplexer is a circuit that selects one of the output lines as shown in fig. 16. when control voltages are more negative, all switches are open and output is zero. when any control voltage becomes zero the input is transmitted to the output.
Intro Exercise – 3

1. In the circuit shown below the parameters are gm = 1 mA /V, ro = 50 k. the gain AV = VO / VS is

(a) – 8.01
(b) 8.01
(c) 14.16
(d) -14.16

1. In the given circuit of figure, if VTH = 0.4 V, the transistor M1 is operating in

(a) linear region
(b) satruation region
(c) M1 is off
(d) cannot be cletermined

1. while biasing JFET, if drain and source are interchanged, then

(a) device will work normally
(b) device will get damaged
(c) device will work but value of ID will get affected
(d) device will not operate at all

1. the values of VC and VGS for the circuit shown in figure are

(a) -2 V, -2 V
(b) 2 V, 2 V
(c) 2 V, -2 V
(d) -2 V, 2 V

1. A three stage cascaded amplifier of identical non-interacting FET common source stage has all over an voltage gain of |1000| and overall bandwidth of 25×106 rad/s.

Given gm = 5 mA /V, the shunt capacitance of each stage is given by
(a) 1.6 pF
(b) 10 pF
(c) 20 pF
(d) 3.2 pF

1. Given, for an FET, gm = 95 mA/V total capacitance is 500 pF. for a voltage gain of – 30, the bandwidth will be

(a) 19 MHz
(b) 6.3 MHz
(c) 100 MHz
(d) 3 MHz

1. in the circuit of figure the transistor parameters are as follows:

Vtp = – 2 V, KP = 1mA/V2 , VSG =?
(a) -3.77 V
(b) 4.37 V
(c) -1.77 V
(d) 1.77 V

1. The p-MOS transistor in figure has parameters

VTP = – 1.2 V, w/L  = 20
and         KP = 30 uA/V2
If ID = 1 mA and VD = – 5 V, then values of RS and RD are
(a) 4 k, 5.8 k
(b) 4 k, 5k
(c) 5.8 k, 4 k
(d) 6.98 k, 5 k
For the circuit shown below transistor parameters are VTN = 2 V, Kn = 0.5 mA/V2 and  = 0. the transistor is in saturation.

1. if IDQ is to be 0.4 mA, the value of VGS,Q is

(a) 5.14 V
(b) 4.36 V
(c) 2.89 V
(d) 1.83 V

1. The value of gm and ro are

(a) 0.89 mS, infinite
(b) 0.89 mS, zero
(c) 1.48 mS, zero
(d) 1.48 mS, infinite

1. (a) The small signal equivalent circuit ia as shown below.

VGS = 50 /50+2 vs
Va = gmVGS (50||10) = -50/52 VS (8.33)
AV = VO / VS = – 8.01

1. (b) For p-channel MOSFET.

VSD (Sat) = VSG + VTH = (1 – 0) – 0.4 = 0.6
VSD = VS – VD = 1 – 0.3 = 0.7
Here,   VSD > VSD (Sat)
So, M1 is in saturation region.

1. (a) The reversibility of terminals is unique in the case of JFET.
2. (a) VGS, Q = – VGG = – 2 V

VGS = VG – VS = – 2 V

1. (b) Gain /stage = 1000 = 10

BW/ stage = 2 x 25 x 106
C = gm / G (BW)
= 5 x 10-3 / 10 x 50 x 106 = 10 pF

1. (b) gm / c = Av x BW

or                  95 x 10-3 / 500 x 10-12 = 30 x BW
or              BW = 6.3 MHz

1. (b) R1 = 10 K, R2 = 20 K, R2 = 1 K, RD = 3 K,

VG = [R2 / R1 + R2] (30) – 15
= (20 / 10 + 20) (30) – 15
= 5 V
Assume transistor is in saturation.
ID = 15 – VS / RS = KP (VSG + VTP)2
15 – VS = RS KP (VSG + VTP)2
where               VS = VG + VSG
15 – (VG + VSG) = (1 x 103) (1 x 10-3) (VSG + VTP)2
15 – 5 – vsg = (VSG + VTP)2
10 –  VSG = (VSG + VTP)2
10 – VSG = (VSG)2 + 2VSG – VTP + (VTP)2
10 – VSG = (VSG)2 – 4VSG + 4
(VSG)2 – 3VSG – 6 = 0
VSG = 4.37 V, – 1.37 V

1. (d) KP = (30 x 10-6 / 2) (20) = 0.3 mA/V2

KP = (KP /2 . w/L)
ID = KP (VSG + VTP)2
1 = 0.3 (VSG – 1.2)2
VSG = 3.02 V, VG = 0
VS = VSG = 3.02 V
ID = 10 – VS / RS
RS = 10 – 3.02 / 1 = 6.98 K
ID = VD – (-10) / RD
RD = – 5 + 10 / 1 = 5 K

1. (c) IDQ = KN (VGS – VTN)2

0.4 = 0.5 (VGS – 2)2
VGD = 2.89 V

1. (a) gm = 2kn (VGS – VTN) = 2 (0.5) (2.89 – 2)

= 0.89 mA/V = 0.89 mS
ro = (IDQ)-1, = 0    ro = 00