# The drain current of a MOSFET in saturation is given by ID = K (VGS – VR)2 where k is a constant. the magnitude of the transconductance gm is

**Unit Exercise – 1**

- The drain current of a MOSFET in saturation is given by I
_{D}= K (V_{GS}– V_{R})^{2}where k is a constant. the magnitude of the transconductance g_{m}is

(a) K (V_{GS} – V_{T})^{2}

**(b) 2K (V _{GS }– V_{T})**

(c) I

_{D}/V

_{GS}– V

_{DS}

(d) K (V

_{GS}– V

_{T }/V

_{GS})

^{2}

**solution and answer :**

- (b) Given, I
_{D}= K (V_{GS}– V_{T})^{2}

Transconductance g_{m} = dI_{d} /dV_{GS}|v_{ds = constant}

= d /dV_{GS} K (V_{GS} – V_{T})^{2}

= 2 K (V_{GS} – V_{T})

**(1 mark questions)**

- In the silicon BJT circuit shown below, assume that the emitter area of transistor Q
_{1}is half that of transistor Q_{2}.

The value of current I_{O} is approximately

(a) 0.5 mA

(b) 2 mA

(c) 9.3 mA

(d) 15 mA

- The amplifier circuit shown below uses a silicon transistor. the capacitor c
_{c}can be assumed to be short at signal frequency and the effect of output resistance r_{o}can be ignored. if c_{e}is disconnected from the circuit which one of the following statements are true?

(a) The input resistance R_{I} increases and the magnitude of voltage gain A_{V} decreases

(b) The input resistance R_{I} decreases and the magnitude of voltage gain A_{V} decreases

(c) Both input resistance R_{I} and the magnitude of voltage gain A_{V} decrease

(d) Both input resistance R_{I} and the magnitude of voltage gain A_{V} increase

- Assuming the op-amp to be ideal, the voltage gain of the amplifier shown below, is

(a) -R_{2}/R_{1}

(b) -R_{3} /R_{1}

(c) -R_{2}||R_{3}/R_{1}

(d) – (R_{2} + R_{3} /R_{1})

- In the following limiter circuit, an input voltage V
_{I}= 10 sin 100 t applied. assume that the diode drop is 0.7 v when it is forward biased. the zener breakdown voltage is 6.8 v.

The maximum and minimum values of the output voltage respectively, are

(a) 6.1 V, – 0.7 V

(b) 0.7 V, – 7.5 V

(c) 7.5 V, – 0.7 V

(d) 7.5 V, – 7.5 V

- The correct full-wave rectifier circuit, is
- In a transconductance amplifier, it is desirable to have

(a) a large input resistance and a large output resistance

(b) a large input resistance and a small output resistance

(c) a small input resistance and a large output resistance

(d) a small input resistance and a small output resistance

- The input impedance (Z
_{I}) and the output impedance (Z_{O}) of an ideal transconductance (voltage controlled current source) amplifier are

(a) Z_{I} = 0, Z_{O} = 0

(b) Z_{I} = 0, Z_{O} = _{00}

(c) Z_{I} = _{00}, Z_{0} = 0

(d) Z_{I} = _{00}, Z_{O} = _{00}

- An n-channel depletion MOSFET has following two points on its I
_{D}– V_{GS}curve

(i) V_{GS} = 0 at I_{D} = 12 mA and

(ii) V_{GS} = – 6 V at I_{D} = 0

Which of the following Q points will give the highest transconductance gain for small signals ?

(a) V_{GS} = -6 V

(b) V_{GS} = + 6 V

(c) V_{GS} = 0

(d) V_{GS} = 3V

- The effect of current shunt feedback in an amplifier is to

(a) increase the input resistance and decrease the output resistance

(b) increase both input and output resistances

(c) decrease both input and output resistances

(d) decrease the input resistance and increase the output resistance

- The input resistance R
_{I}of the amplifier shown in figure, is

(a) 30/4 k

(b) 10 k

(c) 40 k

(d) infinite

- The cascode amplifier is a multi-stage configuration of

(a) CC-CB

(b) CE-CB

(c) CB-CC

(d) CE-CC

- If for a silicon n-p-n transistor, the base to emitter voltage (V
_{BE}) is 0.7 v and the collector to base voltage (V_{CB}) is 0.2 v, then the transistor is operating in the

(a) normal active mode

(b) saturation mode

(c) inverse active mode

(d) cut-off mode

- An ideal op-amp is an ideal

(a) voltage controlled current source

(b) voltage controlled voltage source

(c) current controlled current source

(d) current controlled voltage source

- Voltage series feedback (also called series shunt feedback) results in

(a) increase in both input and output impedance

(b) decrease in both input and output impedances

(c) increase in input impedance and decrease in output impedance

(d) decrease in input impedance and increase in output impedance

- The circuit given in figure is a

(a) low-pass filter

(b) high-pass filter

(c) band-pass filter

(d) band-reject filter

- Assuming V
_{CE, SAT}= 0.2 V and B = 50, the minimum base current (I_{B}) required to drive the transistor in figure to saturation is

(a) 56 uA

(b) 140 uA

(c) 60 uA

(d) 3 uA

- Choose the correct match for input resistance of various amplifier configurtions shown below.

**Configuration input resistance**

CB = Common base LO = Low

CC = Common collector MO = moderate

CE = Common emitter HI = high

(a) CB-LO, CC-MO, CE-HI

(b) CB-LO, CC-HI, CE-MO

(c) CB-MO, CC-HI, CE-LO

(d) CB-HI, CC-LO, CE-MO

- The circuit shown in figure below is best described as a

(a) bridge rectifier

(b) ring modulator

(c) frequency discriminatory

(d) voltage doubler

- If the input to the ideal comparator shown in figure below is a sinusoidal signal of 8 v (peak to peak) without any DC component then the output of the comparator has a duty cycle of

(a) 1/2

(b) 1/3

(c) 1/6

(d) 1/12

- If the differential voltage gain and the common mode voltage gain of a differential amplifier are 48 dB and 2 dB respectively then its common mode rejection ratio is

(a) 23 dB

(b) 25 dB

(c) 46 dB

(d) 50 dB

- Generally, the gain of a transistor amplifier falls at high frequencies due to the

(a) internal capacitance of the device

(b) coupling capacitor at the input

(c) skin effect

(d) coupling capacitor at the output

- In a negative feedback amplifier using voltage-series (i.e.,) voltage-sampling series mixing feedback.(R
_{I}and R_{O}denote the input and output resistances respectively)

(a) R_{I} decreases and R_{O} decreases

(b) R_{I} decreases and R_{O} increases

(c) R_{I} increases and R_{O} decreases

(d) R_{I} increases and R_{O} increase

- A 741-type op-amp has a gain bandwidth product of 1 MHz. A non-inverting amplifier using this op-amp and having a voltage gain of 20 dB will exhibit a 3 dB bandwidth of

(a) 50 kHz

(b) 100 kHz

(c) 1000/17 kHz

(d) 1000/7.07 kHz

- Three identical RC coupled transistor amplifiers are cascaded. if each of the amplifiers has a frequency response as shown in figure, the overall frequency response is as given in
- The current gain of a BJT is

(a) g_{m}r_{o}

(b) g_{m}/r_{o}

(c) g_{m}r

(d) g_{m}/r

- MOSFET can be used as

(a) current controlled capacitor

(b) voltage controlled capacitor

(c) current controlled inductor

(d) voltage controlled inductor

- The ideal op-amp has the following characteristics

(a) R_{I} = _{00}, A = _{00}, R_{O} = 0

(b) R_{I} = 0, A = _{00}, R_{O} = 0

(c) R_{I} = _{00}, A = _{00}, R_{O} = 0

(d) R_{I} = 0, A = _{00}, R_{O} = _{00}

- Consider the following two statements :

**Statement 1** A stable multi-vidrator can be used for generating square wave.

**Statement 2** Bi stable multi-vibrator can be used for storing binary information.

(a) only statement 1 is correct

(b) only statement 2 is correct

(c) both the statements 1 and 2 are correct

(d) both the statements 1 and 2 are correct

- For the ring oscillator shown in figure the propagation delay of each inerter is 100 ps. what is the fundamental frequency of the oscillator output?

(a) 10 MHz

(b) 100 MHz

(c) 1 GHz

(d) 2 GHz

- In the differential amplifier shown in figure, if the source resistance of the current source I
_{EE}is infinite then the common mode gain is

(a) zero

(b) infinite

(c) indeterminate

(d) V_{m1} + V_{m2} /2V_{EE}

- In the circuit of figure below V
_{O}is

(a) -1 V

(b) 2 V

(c) +1 V

(d) +15 V

- An amplifier with resistive negative feedback has two left half plane poles in its open-loop transfer function. the amplifier

(a) will always be unstable at high frequencies

(b) will be stable for all frequencies

(c) may be unstable, depending on the feedback factor

(d) will oscillate at low frequencies

- If the op-amp in figure below is ideal, then V
_{O}is

(a) zero

(b) (V_{1} – V_{2}) sin _{00}t

(c) – (V_{1} + V_{2}) sin _{00}t

(d) (V_{1} + V_{2}) sin _{00}t

- The configuration of figure below is a

(a) precision integrator

(b) hartley oscillator

(c) butter-worth high-pass filter

(d) wien bridge oscillator

- A ssume that op-amp of figure below is ideal. if V
_{I}is a triangular wave, then V_{O}will be,

(a) square wave

(b) triangular wave

(c) parabolic wave

(d) sine wave

- For the same AC voltage and load impedance, which of the following statements about rectifier is courrect ?

(a) the average load current in a full-wave rectifier is twice that in a half-wave rectifier

(b) the average load current in a full-wave rectifier is n times in a half-wave rectifier

(c) half-wave rectifier will have a bigger sized transforms compared to full wave rectifier

(d) half-wave rectifier will have a small sized transformer compared to a full wave rectifier

- Referring to the figure below. the swithc S is in position 1 initially and steady state conditions exist from time t = 0 and t = t
_{o}. the switch is suddenly thrown into position 2. the current I through the 10 k resistor as a function of time t from t = 0, is (give the sketch showing the magnitudes of the current at t = 0, t = t_{o}and t =_{00})

(a) 1 mA

(b) 2 mA

(c) 3 mA

(d) 4 mA

- In figure below the input V
_{I}is a 100 Hz triangular wave having a peak amplitude of 2 V and an average value of zero volt. given that the diode is ideal, the average value of the output V_{O}is

(a) 0.7

(b) 0.6

(c) 0.5

(d) 0.4

- In the circuit of figure below assume that the diodes are ideal and the meter is an average indicating ammeter. the ammeter will read

(a) 0.4 2A

(b) 0.4 A

(c) 0.8 A

(d) 0.4 A

- half-wave rectifier uses a diode with a forward resistance R
_{F}. the voltage is V_{M}sin_{00}t and the load resistance is R_{L}. the DC current is given by

(a) V_{M}/2R_{L}

(b) V_{M} /(R_{F} + R_{L})

(c) 2V_{M}

(d) V_{M }/ R_{L}

- For small signal AC operation a practical forward biased diode can be modeled as

(a) a resistance and a capacitance in series

(b) an ideal diode and resistance in parallel

(c) a resistance and an ideal diode in series

(d) a resistance

- A transistor having a = 0.99 and V
_{BE}= 0.7 is used in the circuit shown in figure below. the value of the collector current will be

(a) 4.327 mA

(b) 5.327 mA

(c) 6.327 mA

(d) 5.508 mA

- The following waveforms shown ……………operation of power amplifier.

(a) class-A

(b) class-B

(c) class-C

(d) class-AB

- Aiter cascading n stages the overall gain becomes,

(a) A/(1 – j f_{1/}f)^{n}

(b) A/(1 – jf/f_{1}) ^{n}

(c) A/(1 – jf/f_{1})^{1/n}

(d) A/ (1 – jf_{1}/f)^{1/n}

- For the circuit given below, the base voltage V
_{B}is

(a)0.8 V

(b) 1.697 V

(c) 1.632 V

(d) 0.721 V

- Consider the circuit shown in figure below. the transistor parameters are B = 100 and V
_{A}=_{00}.

If Q point is in the centre of the load the ilne and I_{CQ} = 0.5 mA the values of V_{BB} and R_{C} are

(a) 20 k, 1.2 v

(b) 10 k, 1.45 v

(c) 48 k, 0.95 v

(d) 48 k, 1.45 v

- The op-amp shown in figure below, has a very poor open-loop voltage gain of 45 but it is ideal. the gain of the amplifier equals

(a) 5

(b) 4.5

(c) 4

(d) 20

- If the transistor parameters are B = 180 and early voltage V
_{A}= 140 V and it is biased at I_{CO}= 2 mA, the values of hybird parameters, g_{m},r and r_{o}are, respectively

(a) 14 A/V, 2.33 K, 90 K

(b) 14 A/V, 90 K, 2.33 K

(c) 77 mA/V, 2.33 K, 70 K

(d) 77.2 A/V, 70 K, 2.33 K

- Voltage gain A
_{V}= V_{C}/V_{S}of the given amplifier circuit is

(a) 750

(b) 150

(c) 50

(d) 100

- A bipolar amplifier circuit shown below, exhibits the following characteristics:

If there is no early effect then voltage gain of the amplifier for a bias current I_{C} = 1 mA is

(a) 20

(b) 40

(c) 10

(d) 100

- If a resistor is introduced in the emitter of a common emitter (CE) amplifier then

(a) both input impedance and voltage gain increase

(b) input impedance increases and voltage gain decreases

(c) input impedance decreases and voltage gain increases

(d) both input impedance and voltage gain decrease

- In the following circuit, voltage drop across R
_{C}and R_{E}are equal to 20 V_{T}and 4V_{T}, respectively. what is the gain of circuit (V_{T}is thermal voltage assume B is high)

(a) -0.25

(b) -4

(c) -5

(d) -1

- In an amplifier response f
_{t}(gain bandwidth product is…………….times greater than f_{b}(lower cut-off) freqeuncy

(a) B

(b) bandwidth

(c) a

(d) none of these

- Transistor transconductance g
_{m}is

(a) directly proportional to current and inversely proportional to temperature

(b) directly proportional to current and directly proportional to temperature

(c) inversaly proportional to current and directly proportional to temperature

(d) inversaly proportional to both current and temperature

- JFET cannot provide high voltage gain because of

(a) low values of u

(b) large values of u

(c) large values of g_{m}

(d) low values of g_{m}

- Consider an n-channel MOSFET with parameters K
_{n}= 0.25 mA/V^{2}, V_{TN}= 1 V, C_{GD}= 0.04 PF and C_{GS}= 0.2 PF. The transistor is biased at V_{GN}= 3 V. the unity gain bandwidth of an FET is

(a) 500 MHz

(b) 350 MHz

(c) 332 MHz

(d) 663 MHz

- A 3 stage cascade amplifier of similar FET CS-stages has an overall voltage gain of |1000| and overall bandwidth of 50 x 10
^{6}Hz. given, g_{m}= 15 mA/V, the shunt capacitance for single stage will be

(a) 15 pF

(b) 150 pF

(c) 0.7 pF

(d)2.4 pF

- The f
_{t}of a BJT is related to its g_{m}, C_{U}and C_{U}as follows

(a) f_{t} = C + C_{U} /g_{m}

(b) f_{t} = e (C + C_{U})/g_{m}

(c) f_{t} = g_{m} /C + C_{U}

(d) f_{t} = g_{m} /2 (C + C_{U})

- From a measurement of the rise time of the output pulse of an amplifier whose input is a small amplitude square wave, one can estimate the following parameters of the amplifier

(a) gain-bandwidth product

(b) slew rate

(c) upper 3 dB frequency

(d) lower 3 dB frequency

- The first dominant pole encountered in the frequency response of a compensated op-amp is approximately at

(a) 5 Hz

(b) 10 kHz

(c) 1 MHz

(d) 100 MHz

- Which of the following circuits are not useful for wave shaping?

(a) clipper

(b) log amplifier

(c) sample and hold circuit

(d) precision rectifier

- The output of the op-amp shown below will be, assuming it to be ideal

(a) zero

(b) – (V_{1} + V_{2})

(c) V_{1} – V_{2}

(d) – (V_{1} – V_{2})

- A boot strap generally incorporates

(a) CE configuration

(b) CB configuration

(c) emitter follower

(d) none of the above

- How can we minimize the errors due to input bias current input offset current?

(a) use the resistance R_{comp} = R_{F}||R_{1}

(b) use of op-amp with small ratings of I_{los}

(c) keep the resistance value as small as possible

(d) all of the above

- The purpose of using R
_{F}in the following circuit is

(a) to reduce the gain at low frequency

(b) to reduce the gain at high frequency

(c) to increases the gain

(d) none of the above

- Applications of precision diode are
- half-wave rectifier
- peak detector
- window detector

which of the above statements are true?

(a) 1, 2 and 3

(b) 1 and 3

(c) 1 and 2

(d) none of these

- The ideal closed-loop voltage gain is

(a) 1

(b) -1

(c) infinite

(d) 50

- A current mirror can be used as an active load because

(a) it has low AC resistance

(b) it has high AC resistance

(c) it has high DC resistance

(d) it has low DC resistance

- V to I converters are used for
- DC and AC voltmeters
- photo devices testing
- AM communication
- diode testing

which of the above staements are true?

(a) 1 and 2

(b) 2 and 4

(c) 1 and 4

(d) 1 and 3

- The op-amp of figure below, has very poor open-loop voltage gain of 45 but is otherwise ideal the gain of the amplifier equals

(a) 5

(b) 20

(c) 4

(d) 4.5

- In order that circuit of figure helow works properly as differentiator it should be modified to ……….(draw the modified circuit)

(c) (a), (b)

(d) none of these

- An op-amp has an offset voltage of 1 mV and is ideal in all other respects. if this op-amp is used in the circuit shown in figure below, the output voltage will be (select the nearest value)

(a) 1 mV

(b) 1 V

(c) = 1 V

(d) zero

- The frequency compensation is used in op-amps to increase its

(a) bandwidth stabilly

(b) frequency gain

(c) amplitude gain

(d) none of these

- The circuit shown in figure below is that of

(a) a non-inverting amplifier

(b) an inverting amplifier

(c) an ocilllator

(d) a schmitt trigger

- One input terminal of high gain comparator circuit is connected to ground and a sinusoidal voltage is applied to the other input. the output of comparator will be

(a) a sinusoidal

(b) a full rectified sinusoidal

(c) a half rectified sinusoidal

(d) a square wave

- The poles of a continuous time oscillators are

(a) imaginary poles

(b) real poles

(c) complex poles

(d) lie on j_{00} axis

- A pulse having a rise time of 40 ns is displayed on a CRO of 12 MHz bandwidth. the rise time of the pulse is observed on the CRO would be approximately equal to

(a) 50 ns

(b) 55 ns

(c) 58 ns

(d) 60 ns

- In a triangular wave generator using comparator integrator so that f
_{o}= 2 kHz and V_{opp}= 7 v, supply voltage = + 15 v, V_{sat}= + 14 v. R_{2}= 10 K and C_{1}= 0.05 uF then determine R_{1}and R_{1}

(a) 40 k, 10 k

(b) 10 k, 40 k

(c) 30 k, 30 k

(d) 5 k, 40 k

- A 1 st order low-pass butter-worth filter has cut-off frequency of 1 kHz for C = 0.01 uF. now, if the cut-off frequncy has to change by a scaling factor of 0.625. what should be the value of resistor ?

(a) 15.9 k

(b) 25.44 k

(c) 9.95 k

(d) 25.47 k

- The phase-shift oscillator in figure below, operates at f = 80 kHz. the value of resistance R
_{F}is

(a) 814

(b) 236

(c) 148

(d) 438

- In a hartley oscillator I
_{1}= 15 mH and C = 50 pF Calculate L_{2}for a frequncy of 168 kHz. the mutuat inductance between L_{1}and L_{2}is 5 uH

(a) 3.1 mH

(b) 2.9 mH

(c) 4.4 mH

(d) 5 mH

- For the circuit shown in figure below the true relation is

(a) V_{01} = 2V_{02}

(b) V_{O1} = V_{O2}

(c) V_{O1} = V_{O1}

(d) 2V_{O1} = V_{O2}

transistor if not given in problem.

- The common-emitter current gain of the transistor is B = 75. the voltage V
_{BE}in on state is 0.7 v.the value of I_{E}and R_{C}are

(a) 1.46 mA, 6.74 k

(b) 0.987 mA, 3.04 k

(c) 1.13 mA, 5.98 k

(d) none of these

- The common-emitter current gain of the transistor is B = 75. The voltage V
_{BE}in on state is 0.7 v. the value of V_{BC}us

(a) 8.4 v

(b) 6.2 v

(c) 4.1 v

(d) none of these

- The circuit shown below is an op-amp based. the ratio V
_{out}/V_{in}is equal to

(a) 9

(b) 10

(c) 21

(d) 11

- In the following circuit of figure below, the region of operation of M
_{1}is (V_{TH}= 0.4 V)

(a) linear

(b)saturation

(c) M_{1} is off

(d) Cannot be determined

**Answers with Solutions**

**Unit Exercise -1**

- (b) Applying voltage law for transistor Q
_{1}

0 – 9.3 x 10^{3} x (I_{ref}) – V_{BE} = – 10

I_{ref} = 10 – V_{BE} /9.3 x 10^{3} = 10 – 0.7/9.3 x 10^{3}

= 1 x 10^{-3} A

I_{0} /I_{ref} = Emitter area of Q_{2} /Emitter area of Q_{1}

I_{0} /I_{ref} = 2

I_{0} = 2 x I_{ref} = 2 x 1 x 10^{-3} = 2 mA

- (c) By disconnecting C
_{E}, the circuit becomes shunt series or current series feedback amplifier. in this case, both output resistance (R_{0}) and voltage gain (A_{V}) will decrease by factor (1 + AB). - (a) The circuit can be re-arranged as

This is an inverting amplifier

Hence, voltage gain (A_{v}) = -R_{2}/R_{1}

- (c) For positive half cycle of input singnal V
_{i}diode D_{1}conducts and D_{2}is reverse biased.

V_{0} = V_{D} + V_{Z} = 0.7 + 6.8 = 7.5 V

For negative half cycle of input signal V_{i} diode D_{1} is reverse biased and D_{2} conducts.

V_{O} = – V_{D} = -0.7

Hence, (V_{max},V_{min}) = (7.5 V,- 0.7 V)

- (b) Given, I
_{D}= K (V_{GS}– V_{T})^{2}

Transconductance g_{m} = dI_{d} /dV_{GS}|v_{ds = constant}

= d /dV_{GS} K (V_{GS} – V_{T})^{2}

= 2 K (V_{GS} – V_{T})

- (c) For positive cycle of input the diode D
_{1}and D_{3}conduct. for negative cycle of input, the diode D_{2}and D_{4}conduct. - (a) A practical transconductance amplifier has large input resistance (R
_{i}>> R_{S}) and presents high output resistance (R_{O}>> R_{L}). - (d) As shown in previous solution the ideal transconductance (voltage controlled current source) amplifier has infinite the input impedance (Z
_{I}) and the output impedance (Z_{o}). - (d)

As shown in curve when V_{GS} is made more, the I_{d} increasing rapidly.

Hence, choosing Q point at V_{GS} = 3 V will give highest transconductance gain.

- (d) the input resistance in curent shunt feedback amplifier

R_{OR} = R_{O} (1 + BA_{I}) hence increases by a factor (1 + BA_{I}).

- (b)

Form virtual ground, V_{A} = 0, I_{S} = V_{S} – V_{A} /10 K = V_{S} /10 K

Input resistance R_{I} = V_{S}/I_{S} = V_{S} /(V_{S}/10 K) = 10 K

12 (b)

In cascode amplifier has common emitter (CE) feeding a common base (CB) .

- ( a) Since, V
_{BE}= 0.7 V, V_{CB}= 0.2 V

The base emitter junction is forward biased and collector base junction is reverse biased. hence, transistor is operating in normal active mode.

- (b) The op-amp output voltage is controlled by input voltage.
- (c) In voltage series feedback amplifier

R_{IF} = R_{I} (1 + BA_{V})

Input resistance increases by a factor (1 + BA_{v}).

R_{OF} = R_{O} / (1 + BA_{V})

Output resistance decreases by a factor (1 + BA_{V}).

- (a)

This is second order low-pass active filter.

- (a)

To drive transistor in saturation,

I_{B} > I_{C,sat} /B

> V_{CC} – V_{CE,sat}/RB

> 3 – 0.2 /1 x 10^{3} x 50 = 56 uA

I_{B} _{min} = 56 uA

- (b) The input impedance of

common base = r_{e}: low, in the range of 20 .

common collector = B (r_{e} + R_{E}) high in the range of 100 k

common emitter = Br_{e} moderate: moderate ; in the range of 1 k.

- (d)

During positive half cycle, diode D_{1} conducts charging capacitor C_{1} to a peak voltage V_{M} and diode D_{2} is non-conducting.

During negative half cycle, diode D_{2} conducts charging capacitor C_{2} to a peak voltage V_{M} and diode D_{1} is non-conducting.

The voltage across capacitors C_{1} and C_{2} is 2V_{m}, hence, the circuit behaves as voltage doubler.

- (c) The given input signal can be expressed as

V_{I} = 4 sin _{00f}

V_{REF} = 2 V

V_{0} = V_{I}; V_{I} > V_{REF}

4 sin _{oof} = 2

sin _{00t} 1/2

_{00t} = 6 , 5/6

Duty cycle = t_{on}/t = 6 – 6 /2 = 4 /12 = 1/3

- (c) common mode rejection ratio (CMRR)

= Differetial voltage gain(A_{D}) /Common mode gain (A_{C})

In decibal, we can write

(CMRR) _{dB} = (A_{d}) _{db} – (A_{C}) _{dB}

= 48 – 2 = 46 dB

- (a) At high frequency internal capacitance effects come into the picture, that’s why it effects the gain of the amplitude.
- (c) In voltage-series feedback amplifier

R_{IF} = R_{I} (1 + BA_{V})

R_{OF} = R_{O} /(1 + BA_{V})

Hence, R_{I} increases and R_{O} decreases by a factor (1 + BA_{V}).

- (b) Given, (Given)
_{dB}= 20 dB

20 log (given) = 20

given = 10

gain bandwidth product = 1 x 10^{6} Hz

gain x 3 dB bandwidth = 1 x 10^{6}

10 x 3 dB bandwidth = 1 x 10^{6}

3 dB bandwidth = 10^{5} Hz = 100 kHz

- (a)

given , lower cut-off frequency f_{l} = 20 Hz

upper cut-off frequency f_{h} = 1 kHz

when n identical amplifiers are cascaded, then overall lower cut-off frequency,

f_{L} = f_{L} /2^{VN} – 1

For n = 3,

f_{l} = 20 /2^{1/3} – 1

= 39.22 – 40 Hz

overall upper cut-off frequency

f^{*}_{H} = f_{H} x 2^{1/n} – 1

n = 3

= 1 x 2^{1/3} – 1

= 0.5 kHz

hence, overall bandwidth decreases.

- (c) small signal model of the BJT

Common emitter current gain B = g_{m}r

where, g_{m} = transconductance

r = small signal resistance between base and emitter.

- (b) In MOSFET, the gate and the channel regions form a parallel-plate capacitor with oxide layer act as a charge on the top plate of capacitor and corresponding opposite charge formed in the induced channel, an electric field thus develop which controls the amount of charge (current) in the channel. hence, MOSFET can be used as voltage controlled capacitor.
- (a) Characteristics of ideal op-amp
- Infinite input impedance
- Zero output impedance
- Zero common-mode gain or infinite common-mode rejection
- Infinite open-loop gain A
- Infinite bandwidth
- (c) Astable multi-vibrator has no stable state and it can be used for generating square wave and triangle waveform.

**Example **oscillator.

Bistable multi-vibrator has two stable output stages. the circuit can remain in either stable state indefinitely and move to another stable state only when appropriately triggered.

**Example** flip-flop (used for storing information).

- (c) Ring oscillator can be formed using odd number of inverter in a loop.

In general, a ring oscillator with N inverters (where, N must be odd will oscillate with period of 2Nt_{p} and frequency 1 /2NT_{P} ; where t_{p} is propagation delay of each inverter.

Here, N = 5; t_{p} = 100 x 10^{-12} s

Fundamental frequency of output

= 1 / 2 x 5 x 100 x 10^{-12}

= 1 x 10^{9} Hz = 1 GHz

- (a)

For differential amplifier

CMRR = A_{D} /A_{C} = 2g_{m}R_{EE}

where, CMRR = Common mode rejection ratio

A_{D} = differential gain

A_{C} = common mode gain

CMRR will be large, if R_{EE} is large.

if R_{EE} _{00}, the CMRR _{ 00} : A_{CM} = 0

i.e., no common mode component appears at the output.

- (d)

As positive feedback is applied hence, the op-amp is forced to operate in saturation region. since, input is applied in positive terminal, output voltage is + V_{SAT}, i.e., + 15 V.

- (c) let two poles exist at s = – a and s = – b.

Hence, open-loop transfer function

G (S) = 1 /(s + a) (s + b)

and H(s) be feedback function.

closed-loop transfer function = V(s + a) (s + b)/1 + H|(s + a) (s + b)

Characteristic equation

= (s + a) (s + b) + h

= s^{2} + (a + b) s + ab + h

roots = -(a + b) + (a + b)^{2} – 4 (ab + h)/2

Hence, closed-loop transfer function depends upon H, amplifier may be unstable for large value of H.

- (c)

from virtual ground concept V_{A} = V_{B} = 0

Applying kirchhoff’s current law at node B,

c d/dt (V_{S} sin _{00t} – 0) + c d/dt (V_{2} sin _{00t} – 0)

= c d/dt ( 0 – V_{o}

d/dt (V_{1} sin _{oot}) + d/dt (V_{2} sin _{00t}) = – d/dt V_{O}

integrating,

V_{0} = – V_{1} sin _{00t} – V_{2} sin _{00t}

= – (V_{1} + V_{2}) sin _{00t}

- (d)

Rearranging the circuit component,

The configuration is wien bridge oscillator, the bridge has series RC network in one arm and a parallel RC network in the adjoining arm. in the remaining two arms of the bridge resistors R_{1} and R_{2} are connected.

Resonant frequency f_{o} = 1 / 2RC

For substained oscillation, R_{2} = 2R_{1},

- (a)

from virtual ground conecept

V_{A} = V_{B} = 0

Applying kirchhoff’s current law at node B,

c d/dt (V_{I} – 0) = (0 – V_{0})/R

V_{0} = – RC dv_{i}/dt

hence, output is differentiation of input waveform, when triangular wave is input, then square wave is output.

- (a)

I_{av} for full wave rectifier = 2I_{m}

I_{av} for half wave rectifier = I_{m}

- (b)

Assume ideal diode at t = 0, t = t_{o}

I = 20/10 k = 2 mA

- (a)

V_{av} = 0.7 V

- (d)

The meter will read during positive half cycle V_{av} = V_{m}/R

= 4 /z x 10 x 10^{3} = 0.4 /z mA

- (b)

V_{m} / z (R_{F} + R_{L})

- (d)

For small signal AC operation practical forward-biased diode equivalent contains a resistor.

- (b)

By KVL

(I_{C} + I_{B}) 1 K + 10 KI_{B} + 0.7 + (I_{B} + I_{C}) 1 K = 12

B = a/1 – a = 0.99 /1 – 0.99 = 99

(I_{C} + I_{C}/99) 10^{3} + 10 x 10^{3} x I_{C} /99 + 0.7 + (I_{C} + I_{C}/99) 10^{3} = 12

100I_{C}/99 x 10^{3} + 10 x 10^{3} x I_{C}/99 + 100I_{C}/99 x 10^{3} +0.7 =12

100 x 10^{3}/99 I_{C} + 10 x 10^{3} I_{C} + 100 x 10^{3}/99 I_{C} = 11.3

I_{C} = 5.327 mA

- (c)

Let V_{1} be the voltage at n-terminals of diode,

V_{1} = 15 x 1/2 + 1 = 5 V

for V_{I} < 5.7 V, V_{0} = V_{I}

V_{1} – 15/2K + V_{1}/1K + V_{0} – V_{I}/1K = 0

3V_{1} + 2V_{0} – 2V_{I} = 15

V_{0} = V_{I} + 0.7

5V_{0} – 2V_{1} = 15 + 2.1 = 17.9

V_{0} = 0.4, V_{I} + 342

- (d)

For V_{S} > 0, when D_{1} is off current through D_{2} is

I = 10 -0.7 /10 + 10 = 0.465 mA

V_{O} = 10ki = 4.65 V

V_{O} = V_{S}, for 0 < V_{S} < 4.65 V

For negative values of V_{S}, the output is negative of positive part.

- (b)

The diode conducts (zero resistance) when V_{I} < 2.5 V and V_{O} = V_{I} Diode is open (2 m resistance) when V_{I} = 2.5 V and V_{O} = 2.5 + V_{I} – 2.5 /3 = 5 V

- (d)

Class AB

- (a)

A/(1 – j f_{i}/f)^{n}

- (b)

The base current I_{B} is

I_{B} = V_{CC} – V_{BE}/R_{B} + BR_{E}

= 10 – 1.6 /3.3 x 10^{6} + 100 x 390 = 2.51 uA

I_{C}~ I_{E} = BI_{B}

V_{E} = 0.251 x 390 = 0.097 V

V_{B} = V_{E} + V_{BE}

= 1.697 V

- (a)

V_{ECQ} = 1/2 V_{CC} 10 V

V_{ECQ} = 20 – I_{CQ}R_{C} = 10

20 – (0.5 mA) R_{C} = 10

R_{C} = 20 K

I_{BQ} = I_{CQ}/B = 0.5 /100 = 5 uA

V_{EB(ON)} + I_{BQ}R_{B} = V_{BB}

0.7 + (5 u)(100 k) = 1.2 V

- (b)

Op-amp shown in the figure has a very poor open loop voltage gain of 45 but otherwise ideal. the gain of amplifier will be

V_{O} = A(V_{L} – V_{A}) = 45(V_{L} – V_{A})

At node, V_{A}/2 + V_{A} – V_{O} /8 = 0

5V_{A} = V_{O}

V_{A} = V_{O}/5

V_{O} = 45 V_{L} – 45V_{A} = 45V_{L} – 9V_{O}

10V_{O} = 45V_{L}

A = V_{O} /V_{L} = 4.5

- (d)

g_{m} = I_{CQ}/V_{T} = 2 m/0.0259 = 77.2 mA/V

r = BV_{T}/I_{CQ} = B/g_{m} = 180/77.2 = 2.33 k

r_{o} = V_{A}/I_{CQ} = 140/2 m = 70 k

- (b)

By DC analysis of the amplifier circuit I_{C} = I_{E} = 0.5 mA (since B is high)

so, V_{C} = 5 – 7.5 x 0.5 = 1.25 V

g_{m} = I_{C}/V_{T} = 0.5 mA/25 mV = 20 mA/V

Small siganal equivalent circuit

V = – V_{I}

Output voltage V_{C} is given as

V_{C} = – V_{M} V x 7.5 = g_{m}V_{S} x 7.5

A_{V} = V_{C}/V_{S} = g_{m} x 7.5 = 20 x 7.5 = 150

- (a)

I_{C} = I_{S} exp (V_{BE}/2V_{T})

Transconductance g_{m} = I_{C}/V_{BE} = I_{C}/2V_{T}

Output impedance

R_{OUT} = R_{C} (since, there is no early effect)

equivalent circuit is

Voltage gain is

|V_{O}/V_{IN}| = g_{m}R_{C} = I_{C}R_{C}/2V_{T} = (1 mA)(1 K)/(2) 0.025 V) = 20

- (b)

CE amplifiers with and without emitter resistance are shown in the following figure

input impedance. R_{IN} = r

input impedance R_{in} [r + (B + 1)]R_{E}

So, emitter degeneration increases the input impedance of CE stage

Voltage gain is

A_{V} = g_{m}R_{C}/R_{C} (with emitter resistance)

A_{V} = R_{C} (with emitter resistance)

1/g_{m} + R_{C}

So, voltage gain decrease.

- (b)

By small signal analysis of the given circuit voltage gain

A_{V} = – R_{C}

1 /g_{m} + R_{E} (B >> 1)

= – R_{C} = – R_{C}I_{C}/R_{E}I_{C} + V_{T}

R_{E} + V_{T}/I_{C}

B is large, so I_{C} ~ I_{E}

A_{V} = – R_{C}I_{C}/R_{E}I_{E} + V_{T}

= -20V_{T}/4 V_{R} + V_{R} = – 20 /5 = -4

- (a)

f_{t} = Bf_{b}

- (a)

g_{m} = |I_{C}|/V_{T}

- (d)

u = g_{m}r_{d} and as g_{m} is very low in JFET, therefore JFET cannot provide high voltage gain.

- (d)

The transconductance is

g_{m} = 2k_{n} (V_{GN} – V_{TN}) = 1 mA/V

The unity gain bandwidth is

f_{t} = g_{m} /2 (C_{gs} + C_{gd}) = 663 MHz

- (d)

gian of 3 stage = 1000

single stage gain = 10

also bandwidth of single stage

= 50 M /2^{1/n} – 1 = 98.07 MHz

2^{1/n} – 1, where n = 3, hence 0.51

now, A_{V} = 10 = g_{m}R_{D}

R_{D} = 666.66

BW ~ f_{h} = 1 /2CR_{D}

C = 1 / 2f_{h}R_{D} = 2.4 pF

- (d)

f_{r} = g_{m}/ 2 (c + c_{u})

- (c)

t_{r} = 0.35/f_{h}

where, f_{h} = upper 3 dB frequency.

- (a)

The first dominant pole encountered in the frequency response of a compensated op-amp is approximately at 5 Hz.

- (b)

Log amplifier has output which is proportional to the logarithm of input voltage where no wave shaping takes place.

- (b)

The circuit acts as an inverting summer

V_{O} = – L /L_{E} V_{1} + L/L V_{2}

= – (L/L_{E} V_{1} + L/L V_{2})

= – (V_{1} + V_{2})

- (c)

A boot strap generally incorporates emitter follower.

- (d)

To minimize error.

R_{comp} = R_{P}||R_{1}, small rating of I_{ios} and running R small.

- (b)

The above circuit is a practical integrator circuit which is used obtain stability in the integrator.

- (c)

Procisio diodes application are half wave rectifier and peak director.

- (a)

V_{+} = V_{I}, V_{– } = V_{I} = V_{O}, V_{O}/V_{I} = 1

- (b)

It has high AC resistance.

- (c)

In DC and AC voltmeters as well as diode testing applications, very little current is required. As input impedance of non-inverting ampliifer is very high, V to I circuit has the advantage of drawing little current from source.

- (d)

op-amp shown in the figure has very poor open loop voltage gain of 45 but it is otherwise ideal. the gain of amplifier will be

V_{O} = A(V_{B} – V_{A}) = 45 (V_{B} – V_{a})

At node V_{A}/2 + V_{A} – V_{O}/8 = 0

5V_{A} = V_{O}

V_{A} = V_{O}/5

V_{O} = 45V_{B} – 45V_{A}

= 45V_{B} – 9V_{O}

10V_{O} = 45V_{B}

A = V_{O}/V_{B} = 4.5

- (a)
- (c)

V_{O} = V_{off} x A_{V}

= 1 x 10^{-3} x 1 M/1 K

= + 1 V

Offset is always + + 1 v

- (a)

Bandwidth stability.

- (d)

V_{A} = R_{2}/R_{1} + R_{2} V_{O}

Output V_{O} will change its stage everytime when input voltage crosses the threshold levels.

V_{UT} = R_{2} /R_{1} + R_{2} x V_{SAT}

V_{LT} = R_{2}/R_{1} + R_{2} x – V_{SAT}

- (d)
- (a)

Imaginary poles

- (a)

Rise time of CRO = 0.35/12 x 10^{6} = 29.17 ns

total time t_{s} = t^{2}_{ro} + t^{2}_{ro}

= (29.17)^{2} + (40)^{2}

= 4.95 x 10^{-8} = 50 ns

- (b)

The peak to peak voltage is given by

V_{OPP} = 2 (R_{2}/R_{3}) V_{SAT}

7 = 2 (R_{2}/R_{3}) (14)

R_{2} = R_{3}/4

R_{2} = 10 K R_{3} = 40 K

Now, the frequency of oscillation is

f_{o} = R_{E}/4R_{1}R_{2}C_{1}

2 K = 40 K/4 x 10 x R_{1}C_{1}

C_{1} = 0.05 uF R_{1} = 10 K

- (c)

The frequency scaling factor is

0.625 = new frequency /original frequency = f_{new}/1 k

f_{new} = 625 Hz

also f_{original } = 1/2RC R = 1/2fC = 15.92 K

R_{new} = (scase factor)*R

= 0.625 x 15.92 k = 9.95 k

- (b)

oscillation frequency,

f = 1/2 6RC

80 K = 1 /2 6R(100)

R = 1/(80 K) (2 6)(100) = 8.12 K

R_{F}/R = 29 [for RC phase shift oscillator, minimum, gain must be 29]

R_{F} = (8.12 K) (29) = 236 K

- (b)

f = 1/2 (L_{eq}C)

L_{EQ} = L_{1} + L_{2} + 2 M

168 x 10^{3} = 1 /2 [L_{eq} x 50 x 10^{-12}]

L_{eq} = 17.95 mH

17.95 x 10^{-3} = 15 x 10^{-3} + L_{2} + 5 x 10^{-6}

L_{2} = 2.945 mH

- (b)

At second stage input to both op-amp circuit is same the upper op-amp circuit is buffer having gain A_{V} = 1. lower op-amp circuit is inverting amplifier having gain

A_{V} = – R/R = -1

V_{01} = – V_{02}

- (c)

I_{E} = 12 – 0.7/10 K I_{E} = 1.13 mA

I_{C} (75/75 + 1) (1.13) = 1.12 mA

V_{CE} = 12 – 1.13 x 10 – 1.12 R_{C} – (-12) = 6 V

R_{C} = 5.98 K

- (c)

8 = 10 x (75 + 1) I_{B} + 0.7 + 10I_{B} – 2

I_{B} = 9.3 /10 + 760 = 12.08 uA

I_{C} = BI_{B} = 0.906 mA

I_{E} = (B + 1) I_{B} = 0.918 mA

8 = 10(0.918) + V_{EC} + 3(0.906) – 8

V_{EC} = 4.1 V

- (d)

V_{O}/V_{IN} = 1 + R_{F}/R_{1}

= 1 + 100 /10 = 1 + 10 = 11

- (b)

In the given circuit

V_{GS} = V_{G} – V_{S} = 1.5 – 0.5 = 1V

V_{DS} = V_{D} – V_{S} = 2 – 0.5 = 1.5 V

V_{DS(SAT)} = V_{GS} – V_{TH} = 1 – 0.4 = 0.6 V

Here, V_{DS} > V_{DS(SAT)} and V_{GS} > V_{TH}

SO, M_{1} is in saturation region

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