A Boolean function Z = ABC is to be implement using NAND and NOR gate. each gate has unit cost.

the minimum number of 2-input nand gates required to implement the boolean function z=abc’ or A Boolean function Z = ABC is to be implement using NAND and NOR gate. each gate has unit cost. ?
Common Data/Linked Answer Questions
Statements for Linked Answer Questions 1 and 2    A Boolean function Z = ABC is to be implement using NAND and NOR gate. each gate has unit cost. only A, B and C are available.

1. If both gate are available then minimum cost is

(a) 2 units
(b) 3 units
(c) 4 units
(d) 6 units

2. If NAND gate are available then minimum cost is

(a) 2 units
(b) 3 units
(c) 4 units
(d) 6 units
Statement for Linked Answer Questions 3, 4 and 5
A MUX network is shown in figure.

3. Z₁ = ?

(a) a + b + c
(b) ab + ac + bc
(c) a . b . c
(d) a * b * c

4. Z₂ = ?

(a) ab + bc + ca
(b) a + b + c
(c) abc
(d) a . b . c

5. This circuit act as

(a) full adder
(b) half adder
(c) full subtractor
(d) half subtractor
Common data for Questions 6 and 7
The building block shown in figure is a active high output decoder.

6. The output X is

(a) AB + BC + CA
(b) A + B + C
(c) ABC
(d) none of these

7. The output Y is

(a) A + B
(b) B + C
(c) C + A
(d) none of these
Statements for linked answer questions 8 and 9
A switching function of four variable, f(w,x,y,z) is equal to the product of two other function f₁ and f₂, of the same variable f = f₁f₂. the function f and f₁ are are follows :
f = m(4, 7, 15)
f₁ = m (0,1,2,3,4,7,8,9,10,11,15)

8. The number of full specified function, that will satisfy the given condition, is

(a) 32
(b) 16
(c) 4
(d) 1

9. The simplest function for f₂ is

(a) x
(b) x
(c) y
(d) y
Common data for Questions 10, 11 and 12
A PLA realization is shown in figure.

10. f₁(x₂,x₁,x₀) = ?

(a) x₂x₀ + x₁x₀
(b) x₂x₀ + x₁x₂
(c) x₂ * x₀
(d) x₂ . x₀

11. f₂ (x₂,x₁,x₀) = ?

(a) m (1,2,5,6)
(b) m (1,2,6,7)
(c) m (2,3,4)
(d) none of these

12. f₃ (x₂,x₁,x₀) =?

(a) IIM (0,4,6,7)
(b) IIM (2,4,5,7)
(c) IIM (1,2,3,5)
(d) IIM (2,3,4,7)
Statement for linked answer Questions 13 and 14
Consider the circuit shown in figure.

13. The expression for the next state Q⁺ is

(a) xQ
(b) xQ
(c) x * Q
(d) x uQ

14. Let the clock pulses be numbered 1,2,3 ……after the point at which the flip-flop is reset (Q₀ = 0). The circuit is

(a) even parity checker
(b) odd parity genertor
(c) both (a) and (b)
(d) none of these
Common data for Questions 15 and 16
The 8-bit left shift register and D flip-flop shown in figure is synchronized with same clock. the D flip-flop is initially cleared.

15. The circuit acts as

(a) binary to 2’s complement converter
(b) binary to gray code converter
(c) binary to 1’s complement converter
(d) binary to excess-3 code converter

16. If initially register contains byte B7, then after 4 clock pulse contents of register will be

(a) 73
(b) 72
(c) 7E
(d) 74
Statement for linked answer Questions 17 and 18
A mealy system produces a 1 output if the input has been 0 for at least two consecutive clocks followed immediately by two or more consecutive 1’s.

17. The minimum state for this system is

(a) 4
(b) 5
(c) 8
(d) 9

18. The flip-flop required to implement this system are

(a) 2
(b) 3
(c) 4
(d) 5
Statements for linked Answer Questions 19 and 20
Two products are sold from a vendingmachine, which has two push buttons p₁ and p₂. when a button is pressed, the price of the corresponding products is displayed in a 7-segment display.
If no buttons are pressed, 2 is displayed, signifying 0.
If only p₁ is pressed, 2 is displayed signifying 2.
If only p₂ is pressed, 5 is displayed, signifying 5.
If both p₁ and p₂ are pressed, E is displayed, signifying error.
The names of the segments in the 7-segment display k, and the glow of the display for 0,2,5 and E are shown below.
Consider
(i) push button pressed/not pressed is equivalent to logic 1/0 respectively.
(ii) A segment glowing/not glowing in the display is equivalent to logic 1/0 respectively.

19. If segments a to g are considered as function of p₁ and p₂ then which of the following is correct?

(a) q = p₁ + p₂, d = c +e
(b) g = p₁ + p₂, d = c + e
(c) q = p₁ + p₂, e = b + c
(d) g = p₁ + p₂, e = b + c

20. What are the minimum numbers of NOT gates and 2-input OR gates required to design the logic of the driver for this 7-segment display?

(a) 3 NOT and 4 OR
(b) 2 NOT and 4 OR
(c) 1 NOT and 3 OR
(d) 2 NOT and 3 OR
Statements for linked Answer Questions 21 and 22
In the following circuit, the comparator output is logic 1 if V₁ > V₂ and is logic 0 otherwise, the D/A conversion is done as per the relations.
V_DAC = 3  2^N-2 V, where b₃(MSB), b₂ , b₁ and b₀ (LSB) are the counter outputs. the counter starts from the clear state.

21. The stable reading of the LED display is

(a) 06
(b) 07
(c) 12
(d) 13

22. The magnitude of the error between V_DAC and V_IN at steady state in volt is

(a) 0.2
(b) 0.3
(c) 0.5
(d) 1.0
Common data for Questions 23 and 24
Consider the resistor transistor logic gate of figure

23. For positive logic the gate is

(a) AND
(b) OR
(c) NAND
(d) NOR

24. For negative logic the gate is

(a) AND
(b) OR
(c) NAND
(d) NOR
Common data for Questions 25 and 26
Consider the DL circuit of figure

25. For positive logic, the circuit is a

(a) AND
(b) OR
(c) NAND
(d) NOR

26. For negative logic, the circuit is a

(a) AND
(b) OR
(c) NAND
(d) NOR
Statement for linked Answer Questions 27 and 28
The input-output voltage specification for the standard TTL family are as follows V_OH(MIN)  = 2.4 V, V_OL(MAX) = 0.4 V, V_IH(MIN) = 2.0 V and V_IL(MAX) = 0.8 V

27. The maximum-amplitude nose spike, that can be tolerated when a high input is driving an input, is

(a) 0.4 V
(b) 0.8 V
(c) 0.2 V
(d) 0.6 V

28. The maximum-amplitude noise spike, that can be tolerated wnen a low output is driving an input, is

(a) 0.4 V
(b) 0.8 V
(c) 0.2 V
(d) 0.6 V
Common data for Qeuestions 29 and 30
Consider the RTL circuit of figure :

29. If V_OT is taken as the output, then circuit is a

(a) AND
(b) OR
(c) NAND
(d) NOR

30. If V₀₂ is taken as the output, then circuit is a

(a) AND
(b) OR
(c) NAND
(d) NOR
Common data for Questions 31 and 32
Consider the circuit of figure

31. If V_O1 is taken as the output, the logic is

(a) AND
(b) OR
(c) NAND
(d) NOR

32. If V₀₂ is taken as the output, the logic is

(a) AND
(b) OR
(c) NAND
(d) NOR
Statements for linked Answer Questions 33, 34 and 35
Consider the AND circuit shown in figure. the binary input levels are V(0) V and V(1) = 25 V. Assume ideal diodes, if V₁ = V(0) and V₂ = V(1), then V₀ is to be at 5V. However if V₁ = V₂ = V(1), then V₀ is to rise above 5 V.

33. If V_SS = 20 V and V₁ = V₂ = V(1), The diode current I_DI, I_D2 and D₀₀ are

(a) 1 mA, 1 mA, 4 mA
(b) 1 mA, 1 mA, 5 mA
(c) 5 mA, 5 mA, 1 mA
(d) 0, 0, 0

34. If V_SS = 40 V and both input are at high level then, diode current I_D1, I_D2 and I_D0 are respectively

(a) 0.4 mA, 0.4 mA, 0
(b) 0,0, 1 mA
(c) 0.4 mA, 0.4 mA, 1 mA
(d) 0, 0, 0

35. The maximum value of V_SS which may be used is

(a) 30 v
(b) 25 v
(c) 125 v
(d) 20 v
Statement for linked Answer Questions 36, 37, and 38

36. When a 74LS device is driving 74ALS input, the noise margins V_NH and V_NL are respectively,

(a) 0.2 v, 0.3 v
(b) 0.3 v, 0.2 v
(c) 0.7 v, 0.3 v
(d) 0.3 v, 0.7 v

37. When a 74ALS device is driving a 74LS input, the noise margin V_NH and V_NL are respectively

(a) 0.4 v, 0.5 v
(b) 0.5 v, 0.4 v
(c) 0.3 v, 0.7 v
(d) 0.7 v, 0.3 v

38. If circuit uses 74LS and 74ALS in combination, then overall noise margin V_NH and V_NL are respectively,

(a) 0.4 v, 0.7 v
(b) 0.7 v, 0.4 v
(c) 0.3 v, 0.5 v
(d) 0.5 v 0.3 v
Common data for Questions 39 and 40
in the circuit of figure each gate is a 74LS series device with I_IH = 20 uA and I_IL = 0.4 mA

39. In high state, the loading on the output of gate 1 is

(a) 2.4 mA
(b) 120 uA
(c) 60 uA
(d) 1.2 mA

40. In low state, the loading on the output of gate 1 is

(a) 0.8 mA
(b) 1.2 mA
(c) 2.0 mA
(d) 2.4 mA
Common data for Questions 41 and 42
Consider the TTL circuit of figure. if either or both V₁ and V₂ are logic low, Q₁ is driven to saturation.

41. The output V₀₁ produces logic

(a) AND
(b) OR
(c) NAND
(d) NOR

42. The output V₀₂ produces logic

(a) AND
(b) OR
(c) NAND
(d) NOR
Statement for linked Answer Questions 43 and 44
In the digital to analog converter circuit shown in the figure below, V_R = 10 V and R = 10 K

43. The current I is

(a) 31.25 uA
(b)62.5 uA
(c) 125 uA
(d) 250 uA

44. The voltage V₀ is

(a) -0.781 v
(b) -1.562 v
(c) -3.125 v
(d) -6.250 v
Common data for Questions 45 and 46

45. The value of V_OUT for an input code of 10110011 would be

(a) 4.28 v
(b) 3.96 v
(c) 4.56 v
(d) 3.58 v

46. The resolution of the DAC is

(a) 0.1%
(b) 0.3%
(c) 0.2%
(d) 0.4%
Common Data/linked Answer Questions

1. (a) Boolean function

Z = ABC
= ABC = ABC = AC + B
Therefore one NAND and one NOR gate is required so, the cost will be 2 unit.

2. (a)

Converting the logic into NAND gate logic
Hence 4 units are required to made a NOR.

3. (d)

The output of first MUX is
Z_O = ab + ab = a * b
The output of first MUX work as a select line for both of the second level MUX, so
S_O = a * b
and   Z₁ = S₀ c + S_Oc
= a * b . c + a * b . c
= (a * b) . c + (a * b) . c
Z₁ = (a * b * c)

4. (a)

Z₂ = BS_O + cS₀
= b(ab + ab) + c(ab + ab) = ab + abc + abc
= a(b + bc) + abc = ab + ac + abc
= ab + ac + bc

5. (a)

output of the first, second level MUX represents the equation of sum of A and B with carry and equation of the second is the resultant carry. thus, this represents a full adder.

6. (a)

The output
X = D₆ + D₇ + D₅ + D₃
= D₃ + D₅ + D₆ + D₇
= ABC + ABC + ABC + ABC
X = AC + AB + BC

7. (d)

Y = D₃ + D₅ + D₁ + D₁
= D₁ + D₃ + D₅ + D₇
= M (1, 3, 5, 7)
Y = C

8. (a)

f₁ = m (1,2,3,4,7,8,9,10,11,15)
f = m(4,7,15)
f = f₁f₂
f₂ = m(4, 7, 15) + d(5, 6, 12, 13, 14)
Because there are 5 don’t care conditions.
so, 2⁵ = 32 different functions f₂.

9. (a)

f₂ = m(4, 7, 15) + dc(5, 6 12, 13, 14)
f₂ = x

10. (c)

f₁ = x₀x₂ + x₀x₁x₂ + x₀x₂
= x₀x₂ (1 + x₁) + x₀x₂            [(1 + x₁) = 1]
= x₀x₂ + x₀x₂
= x₀ * x₂

11. (b)

f₂ = x₀x₁ + x₁x₂ + x₀x₁x₂
= x₀x₁x₂ + x₀x₁x₂ + x₁x₂x₀ + x₁x₂x₀ + x₀x₁x₂
= x₂x₁x₀ + x₂x₁x₀ + x₂x₁x₀ + x₂x₁x₀          [x₂x₁x₀ + x₂x₁x₀ = x₂x₁x₀]
f₂(x₂,x₁,x₀) = m(1, 2, 6,7)

12. (c)

f₃ = x₀x₁ + x₁x₂
= x₂x₁x₀ + x₂x₁x₀ + x₂x₁x₀ + x₂x₁x₀
f₃(x₂ x₁ x₀) = m(0, 4, 6, 7)
f₃(x₂ x₁ x₀) = IIM(1,2,3,5)

13. (c)

Truth table for next state Q⁺
Q⁺ = xQ + xQ
Q⁺ = x * Q

14. (d)

Next state is given as
Q⁺ = x * Q
Q⁺₁ = x₁ * Q₀ = x₁0 + x₁0 = x₁
Q₂⁺ = x₂ * x₁, Q⁺₃ = x₃ * x₂ * x₁
Q₄⁺ = x₄ * x₃ * x₂ * x₁
so, this circuit is used to generate even parit and for checking odd parity.

15. (b)

let initially Q = 0, and the output of the XOR gate is Y.
after first clock
Y = B₇ * 0 = B₇
after second clock
Y = B₇ * B₆
After third clock
Y = B₇ *B₅
After fourth clock
Y = B₅ * B₄
Hence, this circuit will work as a binary to gray code converter.

16. (c)

if register contain byte B7 then,
B7 = 10110111
After first clock pulse
Y = B₇ * 0 = 1 * 0 = 1 B’₃
After second clock pulse
Y = B₇ * B₆ = 1 * 0 = 1 = B₂
After third clock pulse
Y = B₆ * B₅ = 0 * 1 = 1 = B’₁
After fourth clock pulse
Y = B₅ * B₄ = 1 * 1 = 0 B’₀
Where b’₃ b’₂ b’₁ b’₀ are the new values of b₃ b₂ b₁ b₀ After shifting.
so, output of the shift register
01111110₂ = 7E₁₆

17. (a)

the state diagram of mealy system is shown below.
so, there are four minimum states.

18. (a)

2ⁿ = 4
n = 2
thus, two flip-flops are required.

19. (b)

As per question, the truth table.
hence,
a = 1
b = p₁p₂ + p₁p₂ = p₂(p₁ + p₁) = p₂
c = p₁p₂ + p₁p₂ = p₁(p₂ + p₂) = p₁
d = 1
e = p₁p₂ = p₁ + p₂
f  = p₁p₂ = p₁ + p₂
g = p₁p₂ = p₁ + p₂

20. (d)

a = 1
b = p₂ = 1 NOT gate required
c = p₁ = 1 NOT gate required
e = p₁ + p₂ = 1 NOR gate required
f = P₁ + P₂ = 1 OR gate required
g = P₁ + P₂ = 1 OR gate required
hence, 2 NOT and 3 OR gates required.

21. (d)

V_DAC + 2^-1B₀ + 2⁰B₁ + 2¹B₂ + 2²B₃
When V_DAC = 6.5 V
The output of AND is zero and hence stable output is 13.

22. (b)

error = V_DAC – V_IN = 6.5 – 6.2 = 0.3 V

23. (d)
24. (c)

when negative logic is used the circuit represents NAND gate function.

25. (a)

for positive logic
so, the circuit will be an AND gate.

26. (b)

for negative logic
so, the circuit will be an OR gate for a negative logic.

27. (a)

A negative noise splike that can drive the actual voltage below 2.0 v if its amplitude is greater than
V_NH = V_OH(MIN) – V_IH(MIN)
= 2.4 – 2.0
= 0.4 V

28. (a)

A positve noise spike can drive the actual voltage above the 0.8 v level if its aplitude is greater than
V_NL = V_IL(MAX) – V_OL(MAX)
= 0.8 – 0.4
= 0.4 V

29. (d)

this truth table shown NOR logic.

30. (b)

the output V₀₂ is the logic complement of V₀₁
Therefore, this is a OR gate.

31. (c)

thus the truth table shows NAND logic.

32. (a)

The Q₃ state is simple an inverter. hence AND logic is represented.

33. (d)

all diodes are in reverse bias hence all diode current are zero.

34. (a)

because V(1) = 25 V, so diode D₁ and D₂ will be on and D₀  will be off. so, I_D1 and I_D2 will be equal and I_D0 will be zero.
calculation of I_D1 and I_D2
V_A = 25 x 20/20.5 + 40 x 05/20.5 = 25.4 v
I_D1 = I_D2 = 25.4 – 25/1 x 10³
= 0.4 mA
l_d1 = 0.4 mA
I_D2 = 0.4 mA
I_D0 = 0

35. (c)

when  V₁ = V (0)
V₂ = V(1)
V₀ = 5 V
Assume D₁ = On D₂ = Off D₀ = On D₂ is reveres biased by 20 v. hence it is off D₂ is forward biased by 5 v. hence, it is on, to have D₀ On I_D0 must be greater than 0.
I_D0 = – (V_SS – 5)/20K + 5 – 0/1 K > 0
-V_SS + 5 + 120 > 0
V_SS < 125 V

36. (c)

because 74LS device is driving the 74ALS so,

36. (c)

because 74LS device is driving the 74ALS so, the noise margin will be calculated as V_NH.
V_NH = V_OH(MIN) – V_IH(MIN)
= 2.7 – 2.0
= 0.7 V
V_NL = V_IL(MAX) – V_OL(MAX)
= 0.8 – 0.4 = 0.4 V

37. (b)

when 74ALS device is driving 74LS the, noise margin will be
V_NH = V_OH(MIN) – V_IH(MIN)
= 2.5 – 2 = 0.5 V
V_NL = V_IL(MAX)  – V_OL(MAX)
= 0.8 – 0.4 = 0.4 V

38. (d)

when circuit usee 74LS and 74ALS in combination then,
overall noise margin V_NH = 0.5 V
V_NL = 0.3 V

39. (b)

because output of gate 1 drives the six input of the next level gates. so, in high state the loading is equivalent to six 74LS input load therefore.
load = 6 x I_IH
= 6 x 20 u = 120 uA

40. (c)

The truth table for various combinations of V₁ and V₂
The truth table represents AND logic

42. (c)

the Q₂ stage is simply an inverter. therefore, the output V₀₂ is the logic complement of V₀₁.

43. (b)

from concept of virtual ground V_A = 0 (Grounded)
henec, current from voltage source
I = V_R/R = 10/10 x10³ = 1 mA
due to symmetry in the branches of circuit, the current division among various branches is
hence, current = I/16 A = 1 mA/16 = 62.5 uA

44. (c)

the voltage V_O = – I_OR
= – (I/16 + I/4)R
= – (5I/16)R
= – 5 x 1 mA x 10 k/16 = – 3.125 v

45. (d)

input                         output
01100100₂ = 100₁₀       2.0 v
10110011₂ = 179₁₀       (x)
x/2  = 179/100
x = 3.58 v

46. (d)

resoltuion = V_FS/2^N – 1 x 100
1/2⁸ – 1 x 100 = 0.4 %