In a full-wave rectifier using two ideal diodes, VDC and Vm are the DC and peak values of the voltage, respectively across a resistive load

SbistudyPosted oninDigital electronicsLeave a comment

45. In a full-wave rectifier using two ideal diodes, VDC and Vm are the DC and peak values of the voltage, respectively across a resistive load. if PIV is the peak inverse voltage of the diode, then the appropriate relationships for this rectifier are

  1. In the voltage regulator shown in figure, the load current can vary from 100 mA to 500 mA. Assuming that the zener diode is ideal (i.e.,) the zener knee current is negligibly small and zener resistance is zero in the breakdown region), the value of R is

(a) 7
(b) 70
(c) 70/3
(d) 14

  1. An amplifier without feedback has a voltage gain of 50, input resistance of 1 k and output resistance of 2.5 k. the input resistance of the current-shunt negative feedback amplifier using the above amplifier with a feedback factor of 0.2, is

(a) 1/11 k
(b) 1/5 k
(c) 5 k
(d) 11 k

  1. In the amplifier circuit shown in figure, the values of R1 and R2 are such that the transistor is operating at VCE = 3 V and IC = 1.5 mA when its B is 150. for a transistor with B of 200, then operating point (VCE,IC) is

(a) (2 V, 2 mA)
(b) (3 V, 2 mA)
(c) (4 V, 2 mA)
(d) (4V, 1 mA)

  1. The oscillator circuit shown in figure has an ideal inverting amplifier. lts frequency of oscillation (in Hz) is

(a) 1/(2 6 RC)
(b) 1/( 2RC)
(c) 1/ (6RC)
(d) 6/ (2RC)

  1. The output voltage of the regulated power supply shown in figure, is

(a) 3V
(b) 6 V
(c) 9 V
(d) 12 V

  1. The action of a JFET in its equivalent circuit can best be represented as a

(a) current controlled current source
(b) current controlled voltage source
(c) voltage controlled voltage source
(d) voltage controlled current source

  1. If the op-amp in figure is ideal, the output voltage VOUT will be equal to

(a) 1 V
(b) 6 V
(c) 14 V
(d) 17 V

  1. Three identical amplifiers with each one having a voltage gain of 50, input resistance of 1 k and output resistance of 250 are cascaded. the opencircuit voltage gain of the combined amplifier is

(a) 49 dB
(b) 51 dB
(c) 98 dB
(d) 102 dB

  1. An ideal sawtooth voltage waveform of frequecy 500 Hz and amplitude 3 V is generated by charging a capacitor of 2 uF in every cycle. the charging requires

(a) Constant voltage source of 3 V for 1 ms
(b) Constant voltage source of 3 V for 1 ms
(c) Constant voltage source of 3 mA for 1 ms
(d) Constant current source of 3 mA for 2 ms

  1. An amplifier using an op-amp with a slew rate (sr) = 1V/us has a gain of 40 dB. if this amplifier has to faithfully amplify sinusoidal signals from DC to 20 KHz without introducing any slew rate induced distortion, then the input signal level must not exceed

(a) 795 mV
(b) 395 mV
(c) 79.5 mV
(d) 39.5 mV

  1. The circuit in figure employs positive feedback and is intended to generate sinusoidal oscillation. if at a frequency fo; B(f) = VF (F) / VO(F) = 1/6 <00, then to sustain oscillations at this frequency

(a) R2 = 5R1
(b) R2 = 6R1
(c) R2 = R1/6
(d) R2 = R1/5

  1. A zener diode regulator in figure is to be designed to meet the specifications IL = 10 mA, VO = 10 V and Vin varies from 30 V to 50 V. the zener diode has VZ = 10 V and Izk (knee current) = 1mA. for satisfactory operation

(a) R < 1800
(b) 2000 < R < 22000
(c) 3700 < R < 4000
(d) R < 4000

  1. The voltage gain AV = VO/VI of the JFET amplifier shown in figure is

(a) + 18
(b) – 18
(c) + 6
(d) – 6

  1. An n-p-n BJT has gm = 38 mA /V, Cu = 10 -14 F, C = 4 x 10 – 13 F, and DC current gain B0 = 90. for this transistor ft and fb are

(a) ft = 1.64 x 108 Hz and fb = 1.47 x 1010 Hz
(b) ft = 1.47 x 1010 Hz and fb = 1.64 x 108 Hz
(c) ft = 1.33 x 1012 Hz and fb = 1.47 x 1010 Hz
(d) ft = 1.47 x 1010 Hz and fb = 1.33 x 1012 Hz

  1. The transistor shunt regulator shown in figure has a regulated output voltage of 10 v, when the input voltage varies from 20 v to 30 v. the relevant parameters for the zener diode and the transistor are VZ = 9.5, VEE = 0.3 V, B = 99. Neglect the current through RB. then, the maximum power dissipated in the zener diode (pz) and the transistor (pt) are

(a) PZ = 75 MW, PT = 7.9 W
(b) PZ = 85 mW, PT = 8.9
(c) PZ = 95 mW, PT = 9.9 W
(d) PZ = 115 mW, PT = 11.9

  1. The oscillator circuit shown in figure is

(a) Hartley oscillator with foscillation  = 79.6 MHz
(b) Colpitts oscillator with foscillation = 79.6 MHz
(c) Hartley oscillator with foscillation = 159.2 MHz
(d) Colpitts oscillator with foscillantio = 159.2 MHz

  1. The inverting op-amp shown in figure has an open-loop gain of 100. the closed-loop gain VO/VS is

(a) – 8
(b) – 9
(c) – 10
(d) – 11

  1. In figure, assume the op-amps to be ideal. the output VO of the circuit is

(a) 10 cos (100t)
(b) 10 cos (100t) dt
(c) 10-4 cos (100t) dt
(d) 10-4 d/dt cos (100t)

  1. In the circuit of figure, assume that the transistor is in active region. it has a large B and its base-emitter voltage is 0.7 V. the value of IC is

(a) indeterminate since RC is not given
(b) 1 mA
(c) 5 mA
(d) 10 mA

  1. If the op-amp in figure has an input offset voltage of 5 mV and an open-loop voltage gain of 10000, then VO will be

(a) zero
(b) 5 mV
(c) + 15 V or – 15 V
(d) + 50 V or – 50 V

  1. The CMRR of the differential amplifier of figure is equal to

(a) infinite
(b) zero
(c) 900
(d) 1800

  1. Which of the following statements is correct for basic transistor amplifier configurations?

(a) CB amplifier has low input impedance and a low current gain
(b) CC amplifier has low output impedance and a low current gain
(c) CE amplifier has very poor voltage gain but very high input impedance
(d) The current gain of CB amplifier is higher than the current gain of CC amplifier

  1. The JFET in the circuit shown in figure has an IDSS = 10 mA and VP = 5 V. the value of the resistance RS for a drain current IDS = 6.4 mA is (select the nearent value)

(a) 150
(b) 470
(c) 560
(d) 1 k

  1. A class-A transformer coupled, transistor power amplifier is required to deliver a power output of 10 w. the maximum power rating of the transistor should not be less than

(a) 5 W
(b) 10 W
(c) 20 W
(d) 40 W

  1. For the 2 N 338 transistor, the manufacturer specifies PMAX = 100 mW at 25o C free air temperature and the maximum junction temperature, Tmax = 1250C its thermal resistance is

(a) 10oC/W
(b) 1000oC/W
(c) 100oC/W
(d) none of these

  1. An amplifier has an open loop gain of 100 and its lower and upper cut-off frequency of 100 Hz and 100 kHz respectively. A feedback network with a feedback factor of 0.99 is connected to the amplifier. the new lower and upper cut -off frequencies are

(a) 10 MHz 1 Hz
(b) 1 Hz, 10 MHz
(c) 10 Hz, 10 Hz
(d) none of these

  1. Match the list I with list ll and find the correct answer using the codes given below the lists.
  2. A power amplifier delivers 50 W output at 50% efficiency. the ambient temperature is 250C if the maximum allowable junction temperature is 1500C, then the maximum thermal resistance that can be tolerated is

(a) 70C/W
(b) 6 0 C/W
(c) 5 0 C/W
(d) 4 0 C/W

  1. A change in the value of the emitter resistance RE in a difference amplifier

(a) affects the difference mode gain AD
(b) affects the common mode gain Ac
(c) affects both Ad to Ac
(d) does not affect neither Ad nor Ac

  1. To obtain very high input and output impedances in a feedback amplifier, the topology mostly used is

(a) voltage series
(b) current series
(c) voltage shunt
(d) current shunt

  1. The common emitter short circuit current gain B of a transistor

(a) is a monotonically increasing function of the collector current IC
(b) is a monotonically decreasing function of IC
(c) increases with IC for low IC reaches a maximum and then decreases with furter increase in IC
(d) is not a function of IC

  1. Match the list l with list ll and find the correct answer using the codes given below the lists.

List l                                                             List ll

  1. Voltage series configuration 1. increase input impedance
  2. current shunt configuration       2. decrease input impedance
  3. increases closed-loop gain
  4. leads to oscillation

Codes
P                                             Q
(a) 2                                               3
(b) 1                                               3
(c) 1                                                4
(d) 4                                                3

  1. In a common emitter BJT amplifier, the maximum usable supply voltage is limited by

(a) avalanche breakdown of base-emitter junction
(b) collector- base breakdown voltage with emitter open (VCBO)
(c) collector – emitter breakdown voltage with base open (VCBO)
(d) Zerer breakdown voltage of the emitter-base junction

  1. A cascade amplifier stage is equivalent to

(a) a common emitter stage followed by a common base stage
(b) a common base stage followed by an emitter follower
(c) an emitter follower stage followed by a common base stage
(d) a common base stage followed by a common emitter stage

  1. In the BJT amplifier shown in figure, the transistor is biased in the forward active region putting a capacitor across RE will

(a) decrease the voltage gain and decrease the input impedance
(b) increase the voltage gain decrease the input impedance
(c) decrease the voltage gain and increase the input impedance
(d) increase the voltage gain and increase the input impedance

  1. A multistage amplifier has a low-pass response with three real poles at s = – 001 – 002 and 003. the approximate overall bandwidth B of the amplifier will be given by

(a) B = 001 + 002 + 003
(b) 1/B = 1/001 + 1/002 + 1/003
(c) B = (001 + 002 + 003) 1/3
(d) B = 0012 + 0022 + 0032

  1. In a shunt-shunt negative feedback amplifier as compared to the basic amplifier

(a) both input and output impedances decrease
(b) input impedance decreases but output impedance decreases
(c) input impedance increases but output impedance decreases
(d) both input and output impedances increase

  1. A distorted sinusoid has the amplitudes A1, A2, A3 ………….. of the fundamental second harmonic, third harmonic, ………. respectively. the total harmonic distortion is

(a) A2 + A3 + ….. / A1
(b) A22 + A32 + ….. / A1
(c) A22 + A32 + ……. / A12 + A22 + A32
(d) A22 + A32 + … / A1

  1. In a differential amplifier , CMRR can be improved by using an increased

(a) emitter resistance
(b) collector resistance
(c) power supply voltage
(d) source resistance

  1. The circuit of figure is an example of feedback of the following type

(a) current series
(b) current shunt
(c) voltage series
(d) voltage shunt

  1. In the MOSFET amplifier of figure and the signal outputs V1 and V2 obey the relationship

(a) V1 = V2/2
(b) V1 = – V2/2
(c) V1 = 2V2
(d) V1 = – 2V2

  1. Two identical FETs, each characterized by the parameters gm and rd are connected in parallel. the composite FET is then characterized by the parameters

(a) gm/2 and 2rd
(b) gm/2 and rd/2
(c) 2gm and rd/2
(d) 2gm and 2rd

  1. Negative feedback in an amplifier

(a) reduces gain
(b) increases frequency and phase distortions
(c) reduces frequency and phase distortions
(d) increases noise

  1. In the cascade amplifier shown in the figure, if the commone -emitter stage (Q1) has a transconductance gm1 and the common base stage (Q2) has a transconductance gm2 then the overall transconductance g (IO / VI) of the cascade amplifier is

(a) gm1
(b) gm2
(c) gm1/2
(d) gm2/2

  1. Crossover distortion behaviour is characteristic of

(a) class-A output stage
(b) class-B output stage
(c) class-AB output stage
(d) common base output stage

  1. An n-p-n transistor (with C = 0.3 pF) has a unity gain cut off frequency ft or 400 MHz at a DC bias current IC = 1 MA . the vaule of its Cu (in pF ) is approximately (VT = 26 mV)

(a) 15
(b) 30
(c) 50
(d) 96

  1. An amplifier has open-loop gain of 100, an input impedance of 1 k and an output impedance 100 a feedback network with a feedback factor of 0.99 is connected to the amplifier in a voltage series feedback mode. the new input and output impedances respectively, are

(a) 10 and 1
(b) 10 and 10
(c) 100 k and 1
(d) 100 k and 1 k

  1. An amplifier is assumed to have a single-pole high-frequency transfer function. the rise time of its output response to a step function input is 35 ns. the upper 3dB frequency (in MHz) for the amplifier to a sinusoidal input is approximately at

(a) 4.55
(b) 10
(c) 20
(d)28.6

  1. the circuit of figure uses an ideal op-amp. for small positive value of Vin the circuit works as

(a) a half- wave rectifier
(b) a differentiator
(c) a logarithmic amplifier
(d) an exponential amplifier

  1. Assume that the operational amplifier in figure is ideal. the current l through the 1 k resistor is

(a) – 4 mA
(b) – 5 mA
(c) – 5 mA
(d) 4 mA
Unit Exercise – 2 answer key with solution 

  1. (d)

As zener current is negligible small and zener resistance is zero.
IL = 12 – 5 /R = 7/R
At    IL = 100 mA,
= 100 mA = 7/R
R = 70
At      IL = 500 mA,
R = 14
Minimun value of R = 14

  1. (b)

In full-wave rectifer,   VDC = 2Vm
PIV  = 2Vm

  1. (a)

the input resistance of current shunt feedback decreases by factor (1 + AB)
RIF + RI/1 + AB = 1 K /1 + 50 x 0.2 = 1/11 k

  1. (a)

For B, = 150
Applying KVL,
VCC – IC1R2 – VCE1 = 0
Putting the value,
R2 = 2 K
IB1 = IC1 /B1 = 1.5 mA/150 = 0.01 mA
For   B = 200,
IC = BIB
= 200 x 0.01 = 2 mA
VCE2 = VCC – IC2 R2
VCE = 2 V

  1. (a)

one RC pair given phase shift 600 and hence total phase shift will be 1800.
this is a RC phase shift oscillator.
f = 1/2  6 RC

  1. (c)

As zener diode is in breakdown.
the voltage of non-inverting terminal is V. From virtual ground concept, the voltage of inverting terminal is 3 V.
hence,   VO  = 60 /20 x 3 = 9 V

  1. (d)

In JFET. the drain current is controlled by the charge induced in the channel by voltage applied at gate terminal. hence, it can be treated as voltage controlled current source.

  1. (b)

From virtual ground concept,
VA = VB = 8/3
Applying KCL at node A,
2 – 8/3 8/3 – VO
1 K = 5 K
V0 = 6 V

  1. (d)

The open circuit voltage gain of combined amplifier,
AV = AV1 . AV2 . AV
= (50)3
Taking logarithmic
20 log AV = 20 log (50)3 = 60 log 50
= 102 dB

  1. (d)

VC = 1/C I|dt
for one time period T.
VC = 1/C | dt
where, T = 1/f = 2 ms
3 = 1/ 2 uF |2X10 I dt
I = 3 mA
The charging requires constant current source of 3 mA for 2 m.

  1. (c)

Slew rate = A x 2 Vm
V = AV m sin 00t
dV/dt = A VM 00 cos 00t
dV/ dt |max SR = AVM 2 fm
= 20 log x = 40
x = 100 =  A
VM = SR / A x 2 fm = 1/ 10-6 x 100 x 2z x 20 x 103
VM = 79.5 mV

  1. (a)

applying KVL at node 1,
BVO – 0 /R1 + BVO x VO /R2 = 0
B (1/R1 + 1/R2) = 1/R2
B x R1 + R2/R1 = 1
R1 (1 + R2/R1) = 1/B = 6
R2/R1 = 5
R2 = 5R1

  1. (a)

VIN – VO/R > IZ + IL (I1)
IZ + IL = I1, when V1= 30 V
30 – 10 /R > (10 + 1) mA = 20/R > 11mA
R < 1818, When VIN = 50 V
40/R > 11 x 10-3
R > 3636, from this R < 1818

  1. (d)

gm = 2 IDSS/VD (1 – VGS/VD)
VG = 0, VS = ID RS
= 1 mA x 2.5  k = 2.5 V
VGS = VG – VS = – 2.5 V
gm = 2 x 10 /5 mA [1 – (-2.5/-5)] = 2 mS
AV = – gmRD
= – 2 mA x 3 k = – 6

  1. (c)

FT = gm/2 (cu + 2)
putting the value FT = 1.47 x 1010 Hz
from the relation
fb hfe < ft
fb = ft/hfe
putting the vlue
FB = 1.64 x 108 Hz

  1. (c)

we can write
IE = IC + IZ
IB < IZ
IC/IB = 99
Hence,   IE = 100 IZ
From the circuit we can write
IZ = 1/100 = 0.01 A
IC = 99IZ = 0.99 A
PZ = VZIZ = 9.5 x 0.01 mW
pt = VCIC = 10 x 0.99 = 9.9 w

  1. (a)

the tank circuit indicated in figure has capacitor divided cicuit with inductor in paraller, hence it is a colpitts oscillator.
Ceq = C1C2/C1 + C2 = 1 pF
f = 1/2 LCeq = 79.6 MHz

  1. (d)

Let Aol be open-loop gain
VO = AOL VL ………………………(1)
Applying KCL at node A,
VS – VI/R1 = VI – VO/R2
Putting the value of VI from eq. (1)
VS – VO|AOL/R1 = VO|AOL – V0/R2
VS = -89/1000 VO
ACL = VO/VS = – 1000/89 = – 11

  1. (a)

0p-amp (1) circuit works as differentiator with time constant.
L /R = 10 x 10-3/10 = 10-3s
op-amp (2) circuit works as integrator with time constant.
RC = 10-3s
hence the final output will be same as input 10 cos (100 t )

  1. (d)

VIN = RL/R1 + R2 x VCC = 5/15 x 15 = 5 V
since, B is large IB = 0, Rin = 5||10
IC = VIN – V /RC = 5 – 0.7 /430 K = 4.3 /0.430 K
= 10 mA

As no input voltage applied and op-amp has VIN (offset) = 5 mV
VO (offset) = AO < VIN (offset)
= 5 mV x 10,000
= 50 V
VO > Vsat
hence, op-amp is in saturation. hence, output voltage is + 50 mV.

  1. (d) CMRR for the differential amplifier will be

node (1) VA – V1/1 + VA – V0/90 = 0
91VA = VO + 90V1
Node (2) VA/100 + VA – V2/1 = 0
10IVA – 100V2 = 100 x 0
101VA = 100V2
VA = 100V2/101
91 x 100V2/101 = V0 + 90V1
VO = 91 x 100/101 V2 – 90V1
V1 = VC + VD/2 and V2 = VC – VD/2
VO = 9100/101 (VC – VD/2) – 90 (VC + VD/ 2)
VO = 9100/101 VO/2 – 9100/101 VD/2 – 90VC/2 – 90VD/2
= 0.099 VC/2 – 90.04 VD
= 0.0495VC – 90.04 VD
AD = 90.04
AC = 0.0495

  1. (a)

common base amplifier has low input inpedance and low current gain.

  1. (a)

IDSS = 10 mA, VP = 5 V
ID = 6.4 mA
ID = IDSS (1 – VGS/VP)2
6.4/10 = (1 – VGS/VP)
0.2 VP = VGS
VGS = 1V
VGS = IDRS
RS = 1/6.4 x 10-3
RS = 156.25
RS = 150

  1. (c)

for class-A n= 50 %
Pmax > PAC x 100 /n = 10 X 100/50 = 20 W

  1. (b)

thermal resistance 0j = Tmax – TA/P = 125 – 25/100mW
= 10000 C/W
The thermal resistance obtained is very high because it is obtained without use of any heat sink.

  1. (a)

AF = AOL/1 + AOLB = 100/1 + 100 x 0.99 = 1
fh = fh(1 + BAOL)
= 100 x 103(1 + 0.99 x 100) = 10 MHz

  1. (d)
  2. (c)

power delivered.
PD = 50 x 50/100 = 25 w
pd = TI = TA/0JE
0JE = 150 – 25/25 = 50 C/W

  1. (b)

change in value of RE in differential amplier affects the common mode gain AC.

  1. (b)

For current -series to pology
ZIF = ZI (1 + BA)
ZOF = ZO (1 + BA)

  1. (c)

common emitter short cicuit current gain B of a transistor increases with IC when IC reaches a maximum value then B decreases with further increase in IC

  1. (b)
  2. (c)

In common emitter BJT amplifer maximum usable, supply voltage is limited by collector emitter breakdown voltage with base open (BVCBO).

  1. (a)

In cascade amplifier, CE followed by CB.

  1. (b)

Given circuit is common emitter circuit in AC analysis, capacitance acorss RE mode
RE = 0
So, RE will not come in AC analysis and gain (voltage gain) increases, but input impedance.
if RE (emitter resistance) present , it will always reduce the gain.

  1. (a)
  2. (b)

input impedance decreases and output impedance increases in short-shunt negatvie feedback. it is also called as voltage shunt feedback.

  1. (b)
  2. (a)
  3. (d)
  4. (a)

from figure, V1/V2 = RD/2/RD = 1/2
V1 = V2/2

  1. (c)

Two identical resistances in parallel give equivalent value that is half of the individual resistance value , i.e., rd/2 and two identical transconducances in parallel get added
equivalent transconductance is 2 gm

  1. (a)
  2. (a)

gm = IO/VI , IO = IE2 = IC1
IC1 = BIB1, IE2 = IC2
IO = BIB1 , VI = IB1 r
IO/VI = BIB1/IB1r
= gm1 = IC1/VI                (as IC1 = BIB1)

  1. (b)

In class-B crossover distortion is produced in output waveform.

  1. (a)

ft = 1/2 RC
1/R = gm IC/VT
ft = IC/2 VT x CU
CU = 1 mA/2 x 26 mV x 400 x 106
CU = 15 pF

  1. (c)

open -loop gain = 100
B = 0.99
Input impedance = 1 k
output impedance = 100 k
voltage series feedback
ZIF = ZI (1 + AB)
= 1 x 103 (1 + 100 x 0.99)
ZIF = 100 K
ZIF = ZO/1 + AB
ZOF = 100/1 + 100 x 0.99)
ZOF = 1

  1. (b)

amplifier has a single pole high frequency transfer function.
rise time to a step function = 35 n
tr x B 00 = 0.35
B 00 = 0.35/35 x 10-9 = 10 MHz

  1. (c)

The given circuit work as logarithmic amplifier

  1. (a)

I1 = I2 = 2 mA
Applying KCL at A.
I2 + IX = IL
2 + IX = VO/RL
IL = VO/RL
VO = – 2 K x – 2 mA = – V
I2 = – 4 /2 = – 2 mA
2 + IX = – 2
IX = – 4 mA

Leave a Reply

Your email address will not be published. Required fields are marked *