advantages of cyclic codes , application Encoder for Cyclic Codes , disadvantages of cyclic codes :-
EXAMPLE 10.23. Obtain the code vectors for the (7, 4) code having G(p) = 1 + p + p3
Solution : (i) The code vectors in the systematic form can be obtained as under :
X =MG … (i)
where M = Message matrix
and G = Generator matrix.
(ii) Let the message vector be 1 0 1 0. Let us use the generator matrix of the previous example to write,
M[m3 m2 m1 m0] = [1 0 1 0]
Therefore, X = MG = [1 0 1 0] equation
Therefore, X = [1 0 1 0: 0 1 1]. Ans.
This is the required code word.
10.14.7. Encoder for Cyclic Codes
diagram
FIGURE 10.34 Symbols used in the block diagram of encoder of cyclic codes.
Working operation of the encoder
The flip-flops (F/F) of figure 10.36 are used to construct a shift register. Operation of all these flip-flops is governed by an external clock, which is not shown in figure 10.36. The flip-flop contents will get shifted in the direction of the arrow corresponding to each clock pulse. The feedback switch is closed and the output switch is connected to the message input. All the flip-flops are initialized to zero state. First k message bits are shifted to the transmitter and also shifted into the shift register. After shifting the k message bits the shift register will contain the (n – k) parity (or check) bits. Therefore after shifting the k Message bits Parity bits message bits, the feedback switch is open circuited and the output switch is thrown to parity bit position. Now with every shift, the parity bits are transmitted over he channel. Thus this encoder generates the code words in the format shown in figure 10.35.
diagram
FIGURE 10.35 Format of the code word.
The encoder thus performs the division operations and generates the remainder. The remainder is nothing but the parity bits. When all the message bits are shifted out, what remains inside the shift register is remainder.
The encoder also consists of modulo-2 adders. The output of the coefficient multipliers i.e., g1, g2 …. etc. are added to the flip-flop outputs to generate the parity bits.
DIAGRAM
FIGURE 10.36 Encoder for an (n, k) cyclic code.
EXAMPLE 10.24. Draw the encoder for a (7, 4) cyclic Hamming code generated by the generator polynomial, G(p) = 1 + p + p3
Solution: The generator polynomial is given by
G(p) = p3 + 0 p2 + p + 1
The generator polynomial of an (n, k) cyclic code is expressed as under :
equation
For a (7, 4) cyclic having code, n = 7 and k = 4.
Therefore, equation
Hence, G(p) = p3 + g2 p2 + g1 p + 1 …(iii)
Comparing equations (i) and (iii), we get obtain
g1 = 1 and g2 = 0 …(iv)
Thus, the encoder for a (7, 4) Hamming code is shown in figure 10.37.
equation
FIGURE 10.37 Encoder for a cyclic Hamming code.
EXAMPLE 10.25. A message 10 11 01 is to be transmitted in cyclic code with a generator polynomial G(d) = d4 + d3 + 1. Obtain the transmitted code word. How many check bits (i.e., parity bits) does the encoded message contain ? Draw the encoding arrangement for the same.
Solution: (i) First, we obtain the message polynomial M(p) i.e.,
M(p) = m0 + m1p + m2p2 + m3p3 + m4p4 + m5p5
(ii) Then, we multiply M(p) by pn-k to obtain pn-k M(p).
(iii) After that, we divide pn-k M(p) by the generator polynomial G(p).
(iv) Lastly, we obtain the code word X as under :
X = [m5, m4, m3, m2, m1, m0 : c3 c2 c1 c0]
(i) The given message is 10 11 01. Therefore, there are 6 message bits.
Thus, k = 6
(ii) The degree of generator polynomial is four. The degree of generator polynomial is equal to the number of parity bits in the code.
Therefore, number of parity bits (n – k) = 4
So, code word length n = k + 4 = 10
(iii) The message polynomial corresponding to the message 10 11 01 = [m5, m4, m3, m2, m1, m0] is given as,
M(p) = m0 + m1p + m2p2 + m3p3 + m4p4 + m5p5 …(i)
Substituting the values of message bits, we obtain
M(p) = 1 + 0p + p2 + p3 + 0 p + p5 …(ii)
(iv) The generator polynomial can be written in the form as under:
G(p)=1 + 0p + 0p2 + p3 + p4 …(iii)
(v) Let us multiply the message polynomial M(p) by pn-k
Since (n – k) = 4; so pn-k = p4
Therefore, p4 M(p) = p4 [1 + 0 p + p2 + p3 + p4 + p5]
or p4 M(p) = p4 + 0p5 + p6 + p7 + 0 p8 + p9 …(iv)
(vi) Now, we divide p4 M(p) by the generator polynomial
The division takes place as under :
equation
equation
equation
(vii) The code word polynomial can be obtained by adding pn-k M(p) to the remainder polynomial C(p).
Thus, X(p) = p4 M(p) + C(p) …(v)
But C(p) = c0 + c1 p + c2p2 + … cn-k-1 pn-k-1 …(vi)
Here, (n-k-1) = (10 + 6 – 1) = 3
Therefore, C(p) = c0 + c1p + c2p2 + c3p3 …(vii)
But we have obtained c(p) = p2, so, comparing the two, we obtain c0 = 0,
c1 = 0, c2 = 1 and c3 = 0
Therefore, Parity bits (c3, c2, c1 c0) = (0 1 0 0) …(viii)
Therefore the code word is given as under :
X = [m5, m4, m3, m2, ml, m0, c3 c2 c1 c0]
Thus, Code word X= [1 0 1 1 0 1 : 0 1 0 0]
And the corresponding code word polynomial is given as under :
X(p) = p9 + 0 p8 + p7 + p6 + 0p5 + p4 + 0 p3 + p2 + 0 p + 0 Ans.
The encoded message consists of 4 check bits or parity bits c3, c2, c1 and c0.
Now, let us draw the encoder for the cyclic code.
The generator polynomial is given as
G(p) = p4 + p3 + 1
or G(p) = p4 + p3 + 0 p2 + 0 p + 1 …(ix)
The generator polynomial of an (n, k) cyclic code is expressed as under :
equation
Substituting n = 10 and k = 6 and n – k = 4 in equation (x), we shall have
equation
or G(p) = p4 + g3 p3 + g2p2 + g2p2 + g1p1 …(xi)
Comparing equations (ix) and (xi) we get,
gl = 0
g2 = 0
and g3 = 1
Therefore, the coding arrangement is shown in figure 10.38.
diagram
FIGURE 10.38 Encoding arrangement.
Advantages of cyclic codes
The advantage of cyclic codes over most of the other codes are as under :
(i) They are easy to encode.
(ii) They possess a well defined mathematical structure which has led to development of very efficient decoding schemes for them.
(iii) The methods c that are to be used for error detection and correction are simpler and easy to implement.
(iv) These methods do not need look-up table decoding.
(v) It is possible to detect the error bursts using the cyclic codes.
Drawbacks of cyclic codes
Even though the error detection is simpler, the error correction is slightly more complicated. This is due to the complexity of the combination logic circuit used for error correction.