know the answer question Consider the CMOS circuit shown, where the gate voltage VG of the n-MOSFET is increased from zero, while the gate voltage of the p-MOSFET is kept constant at 3 V ?

**Common**** Data/Linked Answer Questions**

**Common** Data for Questions 1 and 2

Consider the common emitter amplifier shown below with the following circuit parameters :

B = 100, g_{m} = 0.3861 A/V

r_{o} = _{oo}, = 259 k, R_{S} = 1K

R_{B} = 93 K, R_{C} = 250

R_{L} = 1K, C_{1} = _{00} and C_{2} = 4.7 mF

- the resistance seen by the source V
_{S}is

(a) 258

(b) 1258

(c) 93 k

(d) infinite

- the lower cut-off frequency due to c
_{2}is

(a) 33.9 Hz

(b) 27.1 Hz

(c) 13.6 Hz

(d) 16.9 Hz

**Statements for linked answer questions 3 and 4**

Consider the CMOS circuit shown, where the gate voltage V_{G} of the n-MOSFET is increased from zero, while the gate voltage of the p-MOSFET is kept constant at 3 V. assume that for both transistors, the magnitude of the threshold voltage is 1 V and the product of the trans conductance parameter and the (W/L) ratio, i.e. the quantity _{u}C_{ox} (W/L) is 1mA/V^{-2}

- For small increase in V
_{G}beyond 1 V, which of the following gives the correct description of the region of operation of each MOSFET?

(a) both the MOSFETs are in saturation region

(b) both the MOSFETs are in triode region

(c) n-MOSFET is in triode and p-MOSFET is in saturation region

(d) n-MOSFET is in saturation and p-MOSFET is in triode region

- Estimate the output voltage V
_{O}for V_{G}= 1.5 V.

**[Hint** Use the appropriate current voltage equation for each MOSFET, based on the answer to question 3]

(a) 4 – 1/2 V

(b) 4 + 1/2 V

(c) 4 – 3/2 V

(d) 4 + 3/2 V

**Statements for linked answer questions 5 and 6**

In the following transistor circuit V_{BE} = 0.7 V, r = 25 mV/I_{E} and B and all the capacitances are very large.

- the value of DC current I
_{E}is

(a) 1 mA

(b) 2 mA

(c) 5 mA

(d) 10 mA

- the mid- band voltage gain of the amplifier is approximately

(a) – 180

(b) – 120

(c) – 90

(d) – 60

**Statements for linked answer questions 7 and 8**

Consider the op-amp circuit shown in the figure.

- the transfer function V
_{0}(s) V_{I}(s) is

(a) 1-sRC/1+sRC

(b) 1 + sRC/1 – sRC

(c) 1/1-sRC

(d) 1/1+ sRC

- If V
_{I}= V_{1}sin (_{00}t) and V_{O}= V_{2}sin (_{00}t +_{0}) then the minimum and maximum values of (in radian) are, respectively

(a) -2/and 2

(b) 0 and 2

(c) – and 0

(d) -2 and 0

**Common data for questions 9, 10 and 11**

In the transistor amplifier circuit shown in the figure below, the transistor has the following parameters

B_{DC} = 60, V_{BE} = 0.7 V, h_{w} – _{00}

the capacitance C_{C} can be assumed to be infinite.

in the figure above, the ground has been shown by the symbol.

- Under the DC conditions, the collector to emitter voltage drop is

(a) 4.8 V

(b) 5.3 V

(c) 6.0 V

(d) 6.6 V

- If B
_{DC}is increased by 10% the collector to emitter voltage drop

(a) increases by less than or equal to 10%

(b) decreases by less than or equal to 10%

(c) increases by more than 10%

(d) decreases by more than 10%

- the small-signal gain of the amplifier is

(a) -10

(b) -5.3

(c) 5.3

(d) 10

In the figure above, the ground has been shown by the symbol.

- the power dissipation in the transistor Q
_{1}shown in the figure is

(a) 4.8 w

(b) 5.0 w

(c) 5.4 w

(d) 6.0 w

- If the unregulated voltage increases by 20%, the power dissipation across the transistor Q
_{1}

(a) increases by 20%

(b) increases by 50%

(c) remains unchange

(d) decreases by 20%

**Common data for questions 14 and 16**

Given, r_{d} = 20 k, I_{DSS} = 10 mA, V_{P} = – 8 V

- Z
_{I}and Z_{O}of the circuit are, respectively

(a) 2 M and 2 k

(B) 2 M and 20/11 k

(c) infinite and 2 k

(d) infinite and 20/11 k

- I
_{D}and I_{DS}under DC conditions are, respectively

(a) 5.625 mA and 8.75 V

(b) 7.500 mA and 5.00 V

(c) 4.500 mA and 11.00 V

(d) 6.250 mA and 7.50 V

- transconductance in milli-siemen (mS) and voltage gain of the amplifier are, respectively

(a) 1.875 mS and 3.41

(b) 1.875 mS and -3.41

(c) 3.3 mS and -6

(d) 3.3 mS and 6

**Statement for linked answer questions 17, 18 and 19**

Consider the circuit shown below, assume that diodes are ideal.

- If V
_{1}= 10 V and V_{2}= 5 V, then output voltage V_{O}is

(a) 9 V

(b) 9.474 V

(c) zero

(d) 8.943 V

- If V
_{1}= V_{2}= 10 V_{,}then output voltage V_{O}is

(a) 9 V

(b) 9.474 V

(c) 4 V

(d) 8.943 V

- If V
_{1}= – 5 V and V_{2}= 5 V, then V_{O}is

(a) 9.474 V

(b) 8.943 V

(c)4.5 V

(d) 9 V

**Statement for linked answer questions 20 and 21**

Consider the circuit shown below. assume diodes are ideal.

- If V
_{1}= V_{2}= 10 V, then output voltage V_{O}is

(a) zero

(b) 9.737 V

(c) 9 V

(d) 9.5 V

- If V
_{1}= -5 V and V_{2}= 10 V, the output voltage V_{O}is

(a) 9 V

(b) 9.737 V

(c) 9.5 V

(d) 4.5 V

**Statement for linked answer questions 22 and 24**

The diodes in the circuit shown below have linear parameters of V_{D} = 0.6 V and r_{f} = 0.

- if V
_{1}= 10 V and V_{2}= 0 V, then V_{O}is

(a) 8.93 V

(b) 7.82 V

(c) 1.07 V

(d) 2.18 V

- If V
_{1}= 10 V and V_{2}= 5 V, then V_{O}is

(a) 9.13 V

(b) 0.842 V

(c) 5.82 V

(d) 1.07 V

- If V
_{1}= V_{2}= 0, then output voltage V_{O}is

(a) 0.964 V

(b) 1.07 V

(c) 10 V

(d) 0.842 V

**Statements for linked answer questions 25 and 26**

the diode in the circuit shown below has the non-linear terminal characteristics as shown in figure. let the voltage be V_{S} = cos _{00}t V.

- the current I
_{D}is

(a) 2.5 (1 + cos _{00}t) mA

(b) 5(0.5 + cos _{oo}t) mA

(c) 5( 1 + cos _{00}t) mA

(d) 5(1 + 0.5 cos _{00}t) mA

- the voltage V
_{D}is

(a) 0.25(3 + cos _{00}t) V

(b) 0.25 (1 + 3 cos _{00}t) V

(c) 0.5 (3 + 1 cos _{00}t) V

(d) 0.5 (2 + 3 cos _{00}t) V

**Statement for linked answer questions 27 and 29**

in the voltage regulator circuit shown below the zener diode current is to be limited to the range 5 < I_{Z} < 100 mA.

- the range of possible load current is

(a) 5 < I_{L} < 130 mA

(b) 25 < I_{L} < 120 mA

(c) 10 < I_{L} < 110 mA

(d)none of these

- the range of possible load resistance is

(a) 60 < R_{L} < 372

(b) 60 < R_{L} < 200

(c) 40 < R_{L} < 192

(d) 40 < R_{L} < 360

- the power rating required for the load resistor is

(a) 576 mW

(b) 360 uW

(c) 480 mW

(d) 75 uW

**Statement for linked answer questions 30 to 32**

for the transistor in circuit shown below B = 200.

- if V
_{B}= 0 V, the value of I_{E}and V_{C}are

(a) 6.43 mA, 2.4 V

(b) 2.18 mA, 3.4 V

(c) 0,6 V

(d) none of these

- If V
_{B}= 1 V, the value of V_{C}is

(a) 4 V

(b) 3 V

(c) 1 V

(d) 1.9 V

- if V
_{B}= 2 V , the value of V_{C}is

(a) – 7 V

(b) 1.5 V

(c) 2.6 V

(d) none of these

**Statement for linked answer questions 33 to 35**

the transistor in circuit shown below has B = 200.

- If V
_{BB}= 0, the value of voltage V_{O}is

(a) 2.46 V

(b) 1.83 V

(c) 3.33 V

(d) 4.04 V

- if V
_{BB}= 1 V , the value of voltage V_{O}is

(a) 4.11 V

(b) 1.83 V

(c) 2.46 V

(d) 3.44 V

- if V
_{BB}= 2 V, the value of voltage V_{O}is

(a) 3.18 V

(b) 1.46 V

(c) 0.2 V

(d) none of these

**Statement for linked answer questions 36 and 37 **

Consider the circuit given in figure below, it is given that I_{SI} = 2 I_{S2} = 5 x 10^{-16} a.

- if I
_{1}= 1.2 mA, the value of V_{B}is

(a) 731.1 mV

(b) zero

(c) 730.6 mV

(d) 1.5 mV

- if circuit is at the edge of active region, what is the value of R
_{C}?

(a) 1475 k

(b) 4.95 k

(c) 0.1 k

(d) none of these

**Statement for linked answer questions 38 and 39**

Consider the transistor amplifier circuit shown below. the transistor parameters are given as B = 100. V_{BE} (on) = 0.7 V. V_{A} = _{00}

- Current gain A
_{I}= I_{O}/I_{1}is

(a) 0.48

(b) 1.00

(c) 0.92

(d) 0.98

- Voltage gain A
_{V}= V_{O}/V_{S}is

(a) 177.1

(b) 345.2

(c) 50

(d) 384.6

**Statement for linked answer questions 40 and 41 **

in the given darlington pair circuit of figure p 120, transistor Q_{1} and Q_{2} parameters are B_{1}r_{1} and B_{2}r_{2} respectively.

- the current gain A
_{I}= I_{O}/I_{1}of the circuit is

(a) B_{1}B_{2}

(b) B_{1} + B_{2}

(c) B_{1} + B_{2} + B_{1}B_{2}

(d) B_{1} + B_{2} – B_{1}B_{2}

- input impedance R
_{IN}is

(a) r_{1} + r_{2}

(b) r_{1} + (1 + B_{1}) r_{2}

(c) B_{1} r_{1} + B_{2} r_{2}

(d) (1 + B_{1}) r_{1} + r_{2}

**Statement for linked answer questions 42 and 43**

for the p-channel transistor in the circuit shown below the parameters are I_{DSS} = 6 mA, V_{P} = 4 V and = 0

- the value of I
_{DQ}is

(a) 8.86 mA

(b) 6.39 mA

(c) 4.32 mA

(d) 1.81 mA

- the value of V
_{SD}is

(a) -4.28 V

(b) 2.47 V

(c) 4.28 V

(d) 2.19 V

**Statement for linked answer questions 44 and 45**

for the following circuit transistor parameters are I_{DSS} = 6 mA, V_{P} = – 6 V, B = 100, V_{BE} = 0.7 V.

- Voltage V
_{C}nearly equals to

(a) 5.67 V

(b) 0.73 V

(c) 1.2 V

(d) 10.93 V

- V
_{DS}is nearly equal to

(a) 11.42 V

(b) 5.75 V

(c) 0.49 V

(d) 10.2 V

**Statement for linked answer questions 46 and 47 **

An n-channel JFET amplifier circuit is shown in figure.

transistor parameters are given as

I_{DSS} = 12 mA, V_{P} = – 4 V = 0.008 V^{-1}

- small-signal transconductance g
_{m}is

(a) 9.01 mA /V

(b) 1.5 mA/V

(c) 4.5 mA/V

(d) 2.98 mA/V

- small-signal voltage gain A
_{V}= V_{O}/V_{S}is

(a) -9.25

(b) -27.72

(c) -4.62

(d) -41.58

**Common data/Linked Answer Questions**

- (b)

the low frequency model

r_{e} = 25 mV/I_{C}

= 2.59

the resistance seen by the source

Z_{IN} = R_{S} + (R_{B}||B_{RE})

= R_{S} + [R_{B} x Br_{e}/R_{B} + Br_{e}

= 10^{3} + (93 x 10^{3} x 100 x 2.59/93 x 10^{3} + (100 x 2.59)

= 10^{3} + 258 – 1258

- (b)

the lower cut-off frequency

f_{l} = 1/2 (R_{L} + R_{C})C_{2}

1/2 (10^{3} + 2.50) (4.7 x 10^{-6})

1/2 x 1250 x 4.7 x 10^{-6} = 27.1 Hz

- (a)

given, that threshold voltage for p-MOS = 1 V

Gate voltage is 3 V. hence, the p-MOS is in active region.

whereas the threshold voltage for n-MOS = 1 V

When gate voltage V_{G} is increased from 1 V. the n-MOS is in saturation.

- (b)
- (a) For DC analysis, all capacitors become open circuited. thevenin equivalent of circuit

When, V_{TH} = 10/10 + 20 x 9 V (from voltage divider rule)

= 3 V

and R_{TH} = 101120 = 10 x 20 /10 + 20 = 6.67 k

As B is very large, I_{B} can be ignored.

Applying KVL in base emitter loop,

V_{TH} – V_{BE} = I_{E}R_{E}

I_{E} = V_{TH} – V_{BE}/R_{E} = 1 mA

- (d)

the small signal model

g_{m} = |I|/V_{T} = I_{E}/V_{T} = 1mA/25 mV = 1/25 A/V

V_{O} = -g_{m}V_{in} (3k ||3k)

= – 1/25 x V_{in} x 1.5 k

A_{V} = V_{O}/V_{IN} = – 60

- (a)

V_{A} = V_{I} x 1/sC

R + 1/sC

V_{A} = 1/1 + sRC = V_{I}

From virtual ground concept

V_{B} = V_{A} = 1/ 1 + sRC = V_{i}

applying KCL at node B,

V_{I} – V_{B} /R_{1} = V_{B} – V_{O}/R_{1}

Putting the value of V_{B},

V_{o} /V_{I} = 1 – sRC/ 1 + sRC

- (c)

As H (S) = V_{O} (s) /V_{I} (s) = 1 – sRC/ 1 + sRC

H (j_{00}) = 1 – j_{00} RC/ 1 + j_{00} RC

LH (i_{00}) = – tan ^{-1} _{00} RC – tan ^{-1} _{00}RC

= – 2 tan^{-1} _{00} RC

AT _{00 } – _{00}

LH (j_{00})_{min }

LH (j_{00}) _{max} = 0

- (c)

Under DC condition, the circuit becomes

Applying KVL in collector emitter circuit,

12 – 1 k (I_{C} + I_{B}) – V_{CE} = 0

and in base loop.

V_{CC} – 1K (I_{C} + I_{B}) – 5I_{B} – V_{BE} = 0

I_{C} = BI_{B}

Solving eqs. (1), (2) and (3), we get

V_{CE} = 5.95 V.

- (b)

As given B increased by 10%.

now, B = 60 + 60 x 10/100 = 66

calculating V_{CE} for B = 66 as in previous question for B = 60

V_{CE} = 5.69 V

% change = 5.69 – 5.95 /5.95 x 100

= – 4.37%

- (a)
- (c)

Zener diode is in breakdown, hence

V_{A} = 6 V

V_{01} = (1 + R_{F}/R_{1}) V_{A} (non-inverting amplifier)

Here, R_{F} = 12 K , R_{1} = 24 K

V_{O1} = 9 V

V_{CE} = 15 – 9 = 6 V

I_{C} = V_{01}/R_{L} = 9/10 = 0.9 A

Power dissipated in Q_{1}

= V_{CE} x I_{C} = 6 x 0.9 = 5.4 W

- (b)

As V_{Z} is 6 V.

the V_{01} and I_{C} will be same.

V_{OR} = 15 + 15 x 20 100 = 18 V

V_{CE} = 18 – 9 = 9 V

P_{D} = V_{CE} x I_{C} = 9 x 0.9 = 8.1 W

% increase = 8.1 – 5.4 /5.4 x 100% = 50%

- (b)

the small signal model

Z_{IN} = 2M

Z_{O} = 20 K||20 K = 20/11 K

- (a)

V_{GS} = – 2 V < 0, hence FET is operating in active region.

I_{D} = I_{DSS} (1 – V_{GS}/V_{P})^{2}

= 10 (1 – (-2)/(-8))^{2} = 5.625 mA

V_{DS} = V_{DD} – I_{D}R_{D}

= 20 – 5.625 x 10^{-3} x 2 x 10^{3} = 8.75 V

- (a)

g_{m} = 2/|V_{P}|I_{D} I_{DSS} = 1.875 mS

A = g_{m} (r_{a}||R_{D})

= 1.875

- (d)

Assume D_{1} On and D_{2} off

then, V_{O} = 9/1 + 9 V_{1} = 9 V

Check assumption

I_{D1} = V_{1} – V_{O}/1 = 10 – 9 = 1 mA > 0

Therefore, D_{1} on

V_{D2} = V_{2} – V_{0}

- (b)

assume D_{1} and D_{2} on,

10/1 + 10 /1

v_{o} = 1/1 + 1/1 + 1/9 = 9.474 V

check assumption

I_{D1} = I_{D2} = V_{1} – V_{O}/1

= 10 – 9.474 /1 = 0.526 > 0

Therefore, D_{1} and D_{2} on,

- (c)

assume D_{1} off and D_{2} on

V_{O} = 9/9 + 1 V_{2} = 9/9 + 1 (5) = 4.5 V

check asspumption

I_{D2} = V_{2} – V_{O}/1 = 5 – 4.5 = 0.5 > 0

therefore, D_{2} on

V_{D1} = V_{1} – V_{O} = – 5 – 4.5 = – 9.5 < 0

Therefore D_{1} off

- (b)

assume D_{1} and D_{2} on

10/1 + 10/1 + 5/9

V_{O} = 1/1 + 1/1 + 9/1 = 9.737 V

1 + 1 + 9

- (c)

assume D_{1} off and D_{2} on,

10/1 + 5/9

V_{O} = 1/1 + 9/1 = 9.5

Check assumption

U_{D2} = 10 – 9.5 /1 = 0.5 A > 0

Therefore D_{2} on

V_{D1} = V_{1} – V_{O} = -5 – 9.5 = – 1.45 < 0

Therefore D_{2} off.

- (c)

D_{1} Will be off and D_{2} Will be on,

10 = 95I + 0.6 + 0.5I

I = 0.94 mA

V_{O} = 10 – 9.5 x 0.94 = 1.07 V

- (c)

D_{1} will be off and D_{2} will be on.

10 = 9.5i + 0.6 + 0.5i + 5 i = 0.44 mA

V_{O} = 10 – 9.4 i = 5.82 V

- (d)

both D_{1} and D_{2} will be on and I_{D1} = I_{D2} = 1/2

10 = 9.5i +0.6 + 0.5 i/2 i = 0.964 mA

V_{O} = 10 – 0.964 (9.5) = 0.842 V

- (c)

the thevenin equivalent circuit for the network to the left of terminal ab is shown below

V_{TH} = 100/200 (2 + cos _{00}t) = 1 + 0.5 cos _{00}t V

R_{TH} = (100)^{2}/200 = 50

The diode can be modeled with V_{F} = 0.5 V and

r_{f} = 0.7 – 0.5 /0.004 = 50

I_{D} = V_{TH} – V_{F}/R_{TH} + r_{f} = 1 + 0.5 cos – 0.5 /50 + 50

= 5 (1 + cos _{oo}t) mA

- (a)

V_{D} = R_{F}I_{D} + V_{F}

= 50 x 5(1 + cos _{oo}t) x 10^{-3} + 0.5

= 0.75 + 0.25 cos _{oo}t = 0.25 (3 + cos _{00}t) V

- (b)

current through 12 resistor is

I = 6.3 – 4.8 /12 = 125 mA

I_{L} = I – I_{Z} = 125 – I_{Z}

25 < I_{L} < 120 mA

- (c)

25 < I_{L} < 120 mA I_{L}R_{L} = 4.8 V

25 < 4.8/R_{L} < 120 mA

40 < R_{L} < 192

- (a)

P_{L} = I_{L}V_{Z} = (120m) (4.8) = 576 mW

- (c)

V_{B} = 0, transistor is in cut-off region

I_{E} = 0, V_{C} = 6 V

- (b)

V_{B} = 1 V. I_{E} = 1- 0.7/1 K = 0.3 mA

I_{C} = I_{E} = 0.3 mA

V_{C} = 6 – I_{C}R_{C} = 6 – (0.3 ) (10) = 3 V

- (b)

V_{B} = 2 V, I_{E} = 2 – 0.7/1 = 1.3 mA

I_{C} = I_{E} = 1.3 mA

V_{C} = 6 – (1.3) (10) = – 7 V

Transistor is in saturation. the saturation voltage

V_{CE} = 0.2 V

V_{E} = (1.3) (1) = 1.3 V

V_{C} = V_{CE} + V_{E} = 1.5 V

- (c)

V_{BB} = 0, Transistor is in cut -off region

V_{C} = R_{L} /R_{C} + R_{L} V_{CC} = 10 (5) /10 + 5 = 3.33 V

- (b)

I_{B} = 1 – 0.7/50K = 6 uA

I_{C} = BI_{B} = 75 x 6u = 0.45 mA

5 – V_{O}/5K = I_{C} + V_{O}/10K

(1 – 0.4) = V_{0}/5 + V_{O}/10

V_{O} = 1.83 V

- (c)

I_{B} = 2 – 0.7/50K = 26 uA

I_{C} = BI_{B} = 75 x 26 uA = 1.95 mA

V_{C} = 5 – I_{C}R_{C} = 5 – 5 x 1.95 = – 4.75 V

Transistor is in saturation,

V_{CE} = 0.2 V = V_{C} = V_{O}

- (c)

from the circuit, we get

I_{1} = I_{C1} + I_{C2}

I_{C1} = I_{S1} e^{vb/v2t}, I_{C2} = I_{S2} e^{ve/vt}

so, I_{1} = I_{S1} e^{ve/vt} + I_{C2} = I_{S2} e^{ve/vt}

= (I_{S1} + I_{S2}) e^{vb/ve}

= (5 x 10^{-16 }+ 5/2 x 10^{-16})e^{vb/vt}

As, I_{S2} = I_{S2}/2 = 5/2 x 10^{-16}

also, I_{1} = 1.2 mA

So, 1.2 x 10^{-3} = 5 x 3/2 x 10^{-16} e^{vb/26×10-3}

V_{T} = 26 x 10^{-3}V

2 x 1.2 x 10^{-3}/15 x 10^{-16} = e^{vb/26×10-3}

2.4 x 10^{13}/15 = e^{vb/26 x 10-3}

V_{B} = 26 x 10^{-3 }in (2.4/15 x 10^{13}) = 730.6 mV

- (b)

by applying KVL

V_{CC} – I_{C}R_{C} – V_{C} = 0

R_{C} = V_{CC} – V_{C}/I_{1}

As, transistor is at edge of active mode.

so, V_{S} = V_{C} R_{C} = V_{CC} – V_{B}/I_{1} = 1475

- (d)

by DC analysis of the circuit

I_{EQ} = 10 – 0.7 /(10K) = 0.93 mA

I_{CQ} = (B/B + 1) I_{EQ} = 100 /101 x 0.93 = 0.921 mA

r = BV_{T}/I_{CQ} = (100)(0.026)/0.921 = 2.82 K

g_{m} = I_{CQ}/V_{T} = 0.921/0.026 = 35.42 mA/V

By small signal AC analysis of the circuit

I_{O} = g_{m}V

apply KCL at emitter

I_{1} = V/T + V_{S}/R_{E} + g_{m}v

I_{1} = V_{S}/R_{E}||r + g_{m}v_{s} = v_{s}(1/R_{E}||r + g_{m})

current gain

A_{I} = I_{O}/I_{1} = g_{m}V_{s} = g_{m}(R_{E}||R) /1 + g_{m} (R_{E} ||r)

= (35.42)(10 k||2.82 k)/1 + (35.42) (10k||2.82 k) = 0.98

- (a)

from small signal AC -equivalent circuit

V_{O } = g_{m}VR_{C }= g_{m}V_{S}R_{C}

A_{O} = V_{O}/V_{S} = g_{m}R_{C}

= (35.42 mA/V)(5 K) = 177.1

- (c)

small signal equivalent circuit of the darlington-pair

V_{1} = I_{1} R_{1}

So, g_{m1}V_{1} = gm_{1} r_{1}i_{1} = B_{1}i_{1} …………………(1)

_{ }(B_{1} = g_{m1} r_{1})

V_{2} = (i_{1} + g_{m1} v_{1}) r_{2} = (i_{1} + B_{1}I_{1}) r_{2} ………………….(2)

putting V_{1} and V_{2} from eqs, (1) and (2)

i_{o} = g_{m1} r_{1}i_{1} + g_{m2} (i_{1} + B_{1}I_{1}) r_{2}

i_{o} = B_{1} i + g_{m2} (i_{1} + B_{1} i_{1}) r_{2}

i_{o} = B_{1} + g_{m2}r_{2} + g_{m2} r_{2} B_{1}

i_{o}/i_{1} = B_{1} + B_{2} + B_{1}B_{2}

So, A_{I} = I_{O}/I_{1} = B_{1} + B_{2} + B_{1}B_{2}

- (b)

from equivalent circuit

V_{S} = V_{1} + V_{2} = i_{1}r_{1} + i_{1} (1 + B_{1})r_{2}

R_{in} = V_{S}/F_{1 }= r_{1} + (1 + B_{1}) r_{2}

- (d)

assume transistor is in saturation

V_{S} = – V_{GS}

I_{D} = 0 – V_{S}/R_{S} = V_{GS}/R_{S} = I_{DSS} (1 – V_{GS}/V_{P})^{2}

R_{S} = 1K

V_{GS}/1 K (6 M) (1 – V_{GS}/4)^{2}

V_{GS} = 8.86, 1.81 V

V_{GS} = 8.86 V is impossible

I_{D} = V_{GS} /R_{S} = 1.81/1K = 1.81 mA

- (b)

V_{D} = I_{D}R_{D} – 5 (1.18m) (0.4 k) – 5 = – 4.276 v

V_{SD} = V_{S} – V_{D} = – 1.81 – (-4.276) = 247 V

V_{SD(SAT)} = V_{P} – V_{GS} = 4 – 1.81 = 2.19 V

V_{SD} > V_{SD(SAT)}

Assumption is correct.

- (a)

assuming base current is zero,

V_{B} = V_{G} = 10K (16)/(40K + 10K) = 3.2 V

V_{E} = V_{B} – V_{BE} = 3.2 – 0.7 = 2.5 V

I_{E} = V_{E}/R_{E} = 2.5/1.2K = 2.08 mA

I_{C} = I_{E} = 2.08 mA

I_{D} = I_{C} = 2.08 mA

V_{C} = V_{G} – V_{GS}

Where, V_{GS} = V_{P} (1 = I_{D}/I_{DSS})

V_{C} = (-6) (1 = 2.08/6) = – 2.47 V

V_{C} = 3.2 – (-2.47) = 5.67 V

- (b)

from the circuit

V_{D} = 16 – I_{D} (2.2) = 11.42 V

V_{DS} = V_{D} – V_{S} = V_{D} – V_{C}

11.42 – 5.67 = 5.75 V

- (d)

By DC analysis of the circuit

V_{GS} = (180/180 + 420) 20 – I_{D} x 2.7

I_{D} = I_{DSS} (1 – V_{GS}/V_{P})^{2}

So, V_{GS} = 6 – I_{DSS} (1 – V_{GS}/V_{P})^{2} x 2.7

V_{GS} = 6 – (12) (2.7) (1 – V_{GS}/(-4)^{2}

2.025 V^{2}_{GS} = 17.2 V_{GS} + 2.4 = 0

V_{GS} = – 2.01 V

transconductance is

g_{m} = 2I_{DSS}/|V_{P}| (1 – V_{GS}/V_{P})

= 2 (12) /4 [1 – (2.01)/(-4) ) = 2.98 mA/V

- (c)

the small signal equivalent circuit of n-channel JFET is the same as n-channel MOSFET

Here, R_{1} = 420 K, R_{2} = 180 K, R_{D} = 2.7 K

R_{L} = 4 K

Voltage gain

A_{V} = V_{O}/V_{S} = – g_{m} (r_{o}||R_{D}||R_{L})

Output resistance

r_{o} ~ 1/I_{D}

BY DC analysis

I_{D} = I_{DSS} (1 – V_{GS}/V_{P})^{2} = 12 (1 – (-2.01)/(-4))^{2}

= – 2.97 mA

So, r_{o} ~ 1/ 0.008 x 2.97 = 42.1 k

A_{V} = – 2.98 (42.1||2.7||4) = – 4.62