comparators are used in | comparators are used in circuits such as | comparator definition meaning

comparators are used in | comparators are used in circuits such as | comparator definition meaning in digital electronics ?
An analog comparator has two inputs one is usually a constant reference voltage VR and other is a time varing signal VI and one output V0. the basic circuit of a comparator is shown in fig. 54.
When the non-inverting voltage is large than the inverting voltage, the comparator produces a high output voltage (+Vsat). When the non-inverting output is less than the inverting input, the output is low (-Vsat).Fig. 54 (b) also shows the output of a comparator for a sinusoidal.
V0 = – Vsat, if Vi > VR
= + Vsat if VI < VR
If VR = 0, then slightest input voltage (in mV) is enough to saturate the op-amp and the circuit acts as zero crossing detector as shown in fig. 54 (c). if the supply voltages are + 15 V, then the output compliance is from approximate -13 V to + 13 V. the more the open-loop gain of op-amp, the smaller the voltage requires to saturate the output. if Vd required is very small then the characteristic is a vertical line as shown in fig. 54(d) and (e).
If we want to limit the output voltage of the comparator two voltage (one positive and other negative) then a resistor R and two zener diodes are added to clamp the output of the comparator. the circuit of such comparator is shown in fig. 67(f) the transfer characteristics of the circuit is also shown in fig. 54(g).
The resistance is chosen, so that the zener operates in zener region when VR = 0, then output changes rapidly from one state to other very rapidly every time that the input passes through zero as shown in fig. 54(h) and (i).
Such a configuration is called zero crossing detector. if we want pulses at zero crossing then a differentiator and a series diode is connected at the output. it produces single pulses at the zero crossing point in every cycle.
If the input to a comparator contains noise, the output may be erractive when Vin is near a trip point. for instance, with a zero crossing, the output is low, when Vin instance, with a zero crossing, the output is low, when VIN is positive and high when VIN is negative. if the input contains a noise voltage with a peak of 1 mV or more, then the comparator will detect the zero crossing produced by the noise. fig. 55(a) shown the output of zero crossing detection, if the input contains noise.
This can be avoided by using a schmitt trigger, circuit which is basically a comparator with positive feedback.
Fig. 55(b) shows an inverting schmitt trigger circuit using op-amp.
Because of the voltage divider circuit, there is a positive feedback voltage. when op-amp is positively saturated a positive voltage is feedback to the non-inverting input, this positive voltage holds the output in high stage (VIN < VF). When the output voltage is negatively saturated, a negative voltage feedback to the inverting input, holding the output in low state.
When the output is +Vsat, then reference Vref is given by
Vref = R1 / (R1 + R2) * Vsat = (+BVsat)
If Vin is less than Vref output will remain +Vsat.
When input Vin exceeds Vref = +Vsat, the output switches from + Vsat to -Vsat. Then, the reference voltage is given by
Vref = -R2 / (R1 + R2) * Vsat = (-BVsat)
The output will remain -Vsat as long as Vin > Vref.
If Vin < Vref, i.e,. Vin becomes more negative than -Vsat, then again output switches to +Vsat and so on. the transfer characteristic of schmitt trigger circuit is shown in fig. 55(c). the output is also shown in fig. 55(d) for a sinusoidal wave. if the input is different than sine even then the output will be determined in a same way.
Positive feedback has an unusual effect on the circuit. if forces the reference voltage to have the same polarity as the output voltage. the reference voltage is positive when the output voltage is high (+Vsat) and negative when the output is low (-Vsat).
In a schmitt trigger, the voltage at which the output switches from +Vsat to -Vsat or vice-versa are called upper trigger point (UTP) and lower trigger point (LTP). the difference between the two trip points is called hysteresis.
UTP = R2 / R1 + R2 = Vset
LTP = R2 / R1 + R2 = (-Vsat)
                   Vhys = UTP – LTP
= R2 / R1 + R2 = Vsat – R2 / R1 + R2 = (-Vsat)
= 2 (R2 / R1 + R2) Vsat
= 2BVsat
The hysteresis loop can be shifted to either side of zero point by connecting a voltage source as shown in fig. 55(e) and (f).
When V0 = +Vsat, the refernce voltage (UTP) is given by,
UTP = (Vsat  -VR)R2 / R1 + R2 + VR
BVsat + R1VR / R1 + R2
When V0 = – Vsat, the reference voltage (UTP) is given by,
LTP = (-Vsat – VR) R2 / R1 + R2 = VR
= – BVsat + R1VR / R1 + R2
If VR is positive, the loop is shifted to right side; if VR is negative, the loop is shifted to left side. the hysteresis voltage Vhys remains the same.
Non-Inverting Schmitt Trigger
In this case, again the feedback is given at non-inverting termilnal. the inverting terminal is grounded and the input voltage is connected to non-inverting input. fig. 56 shows an non-inverting schmitt trigger circuit.
To analyze the circuit behaviour, let us assume the output is negatively saturated. then, the feedback voltage is also negative (-Vsat). This feedback voltage will hold the output in negative saturation untill the input voltage becomes positive enough to make voltage positive.
V+ = (-Vsat – Vin) /R1 + R2 = R2 + VIN
= -VsatR2 / R1 + R2 + VINR1 /R1 + R2
= R1 / R1 + R2 (-R2Vsat + R1VIN)
= R1 /R1 + R2 (R2Vsat / R1 = Vin)
When VIN becomes positive and its magnitude is greater than (R2 / R1)Vsat, then the output switches to +Vsat. therefore, the UTP at which the output switches to +Vsat is given by.
UTP = (R2Vsat /R1)
Similarly, when the output is in positive saturation, feedback voltage is positive. to switch output state, the input voltage has to become negative enough to make. when it happens the output changes to the negative state from positive saturation to negative saturation voltage negative.
V+ = (Vsat – VIN)/ R1 + R2 = R2 + Vin
= Vsat R2 / R1 + R2 + Vin R1 / R1 + R2
= R1 / R1 + R2 (R2Vsat + R1Vin)
= R1 / R1 + R2 (R2 Vsat / R1 + Vin)
When, Vin becomes negative and its magnitude is greater than R2/R1 Vsat, then the output switches to -Vsat.
LTP = (-R2Vsat / R1)
The difference of UTP and LTP given the hystersesis of the schmitt trigger.
Vbys = UTP – LTP
= 2 (R2/R1) Vsat
= 2BVsat
In non-inverting schmitt trigger circuit, the B is defined as
B = R2/R1
Example 14. Design a voltage level detector with noise immunity that indicates when an input signal crosses the nominal threshold of -2.5 V. the output is to switch from high to low, when the signal crosses the threshold in the positive direction and vice-versa. noise level expected is 0.2 VPP maximum assume the output levels are VH = 10 V and VL = 0 V.
Sol. for the triggering action required an inverting configuration is required. let the hysteresis voltage be 20% larger than the maximum pp noise voltage that is Vhys = 0.24 v.
Thus, the upper and lower trigger voltages are – 2.5 + 0.12 or UTP = 2.39 V and LTP = – 2.62 V
Since, the output levels are VH and VL instead of + Vsat and -Vsat, therefore, hysteresis voltage is given by
Vhys = R2 / R1 + R2 (VH – VL)
Or                             VH – VL / Vhys = 1 + R1 / R2
and                       R1/R2 = 10 – 0/0.24 – 1 = 40.7
The reference voltage Vref can be obtained from the expression of LTP.
LTP = BVL + R1Vref / R1 + R2
Given that VL = 0 and LTP = – 262, we obtain
VR = (1 + R2/R1) LTP = (1 + 1/40.7) (-2.62) = – 2.68 V
We can select any values for R2 and R1 that satisfy the ratio of 40.7. it is a good practice to have more than 100 k for the sum of R1 and R2 and 1 k to 3 k for the pull-up resistor on the output. the circuit shown in figure above shows a possible final design. the potentiometer serves as a fine adjustment for VR while the voltage follower makes VR to appear as an almost ideal voltage source.
Relaxation Oscillator
With positive feedback, it is also possible to build relaxation oscillator which produces rectangular wave.
The circuit is shown in fig. 57(a).
In this circuit a fraction R2/(R1 + R2) = B to the output is feedback to the non-inverting input terminal. the operation of the circuit can be explained as follows:
Assume that the output voltage is +Vsat. the capacitor will charge exponentially toward +Vsat. the feedback voltage is +bVsat. when capacitor voltage exceeds + bVsat the output switches from + Vsat to -Vsat. then feedback voltage becomes -Vsat and the output will remain -Vsat. now, the capacitor charges in the reverse direction. when capacitor voltage decreases below – bVsat (more negative than -bVsat) the output again switches to +Vsat. this process continues and it produces a square wave. under steady state conditions, the output voltage and capacitor voltage are shown in fig. 57 (b). the frequency of the output can be obtained as follows.
The capacitor charges from -BVsat to +BVsat during time period T/2. the capacitor charging voltage expression is given by
VC (t) = {Vsat – (-BVsat)} (1 – e-t/RC) -BVsat
At                               T = t/2, VC (t) = +BVsat
BVsat = (1 + B) Vsat (1- e-t/2RC) – BVsat
2B = (1 + B) (1 – e-t/2RC)
Or                        1 – e-t/2RC = 1B/1 + B
Or                       e-t/1RC = 1 – B/1 + B
Or                     e-t/RC = 1 + B/1 – B
Or                      t/2RC = 1n 1 + B/1 – B
Or                         t = 2RC 1n (1 + B / 1 – B)
The frequency of the output is given by f = 1 / t
f = 1 / t = 1 / 2RC 1n (1 + B /1 – B)
This square wave generator is useful in the frequency range of 10 Hz to 10 KHz. at higher frequencies, the slew rate of the op-amp limits the slope of the output square wave.
The duty cycle of the output wave can be changed replacing the resistance R by another circuit consisting of variable resistance and two diodes D1 and D2 as shown in fig. 57 (c).
When the output is positive then D2 conducts and D1 is off. the total feedback resistance becomes Rb + R and charging voltage is reduced by VD. During the interval when the output is negative than D1 conducts and D2 is off. the charging resistance becomes R + RA. the total charging and reverse charging period is decided by total resistance (2R + RA + RB) = constant. therefore, frequency will remain constant but duty cycle changes. the capacitor voltage and output valtage of the oscillator are shown in fig. 57 (d).
t1 = (R + RB) C 1n (1 + B/1 – B)
t2 = (R + RA) C 1n (1 + B/1 – B)
t = t1 + t2 = (2R + RA + RB) C 1n (1 + B/1 – B)
The duty cycle is given by D = t1 / t = R + RB / 2R + RA + RB
BY varying RA and RB the duty cycle can be charged keeping frequency constant.
Triangular Wave Generator
In the relaxation oscillator, capacitor voltage VC has a near triangular wave shape but the sides of the triangles are exponential rather than straight line. to linear size the triangles, if is required that C be charged with a constant current rather that the exponential current through R. the improved circuit is shown in fig. 58(a).
In this circuit an op-amp integrator is used to supply a constant current to C, so that the output is linear. because of inversion through the integrator, this voltage is feedback to the non-inverting terminal of the comparator rather than to the inverting terminal. the inverter behaves as a non-inverting schmitt trigger. the voltage VR is used to shift the DC level of the triangular wave and voltage VS is used to change the slopes of triangular wave form is shown in fig. 58(b).
To find the maximum value of the triangular waveform assume that the square wave voltage Vo is at its negative value = – Vsat. with a negative input, the output V(t) of the integrator is an increasing ramp. the voltage at the non-inverting comparator input V1 is given by.
V1 = (-Vsat – Vout / R1 + R2) R2 + Vout
Or          V1 = R1 / R1 + R2 = Vout – R2 / R1 + R2 = Vout
When V1 rises to VR, the comparator changes state from -Vsat to +Vsat and V(t) starts decreasing linearly similarly,when V1 falls below VR, the comparator output changes from +Vsat to -Vsat.
Hence, the minimum value of triangular Vmin occurs for V1 = VR. hence, the pecak value Vmax of the triangular waveform occurs for V1 = VR.
Therefore,       Vmax = R1 + R2 / R1 = VR + R2 / R1 = Vsat
And                  Vmin = R1 + R2 / R1 = VR – R2/ R1 = Vsat
The peak to peak swing is given by
Vmax – Vmin = 2Vsat R2/R1
The average output voltage is given by VR (R1 + R2 / R1).
If VR = 0, the waveform extends between -Vsat (R2/R1) and +Vsat (R2/R1).
The sweep times t1 and t2 for VS = 0 can be calculated as follows :
The capacitor charging current is given by
I = C dVC / dt = – C dVout / dt
Where, VC = – Vout is the capacitor voltage.
For                      Vout = – Vsat,       I = – Vsat / R
Therefore,            -Vsat / R = – C dVout / dt
dVout / dt = Vsat / RC
Or                              Vmax – Vmin / t1 = Vsat / RC
Therefore,                t1 = Vmax – Vmin / Vsat / RC
When the output voltage of first op-amp is +Vsat, then the voltage V1 is given by
V1 = (-Vsat – Vout / R1 + R2 = R2 + Vout
As triangular voltage increases, the voltage V1 also increases. At t = t1, when the voltage Vout become Vmax the voltage V1 becomes equal to VR and switching takes place. Therefore,
VR = -VsatR2 / R1 + R2 + R1 / R1 + R2 =  Vmax
Or                         Vmax = R1 + R2 / R1 = VR + R2 / R1 = Vsat
Similarly, when output voltage is +Vsat, then voltage V1 is given by
V1 = (Vsat – vout ) / R1 + R2 = R2 + Vout
As triangular voltage decreases, the voltage V1 also decreases. At t = t2, when the voltage Vout becomes Vmin, the voltage V1 becomes equal to Vg and switching takes place. therefore,
VR = Vsat R2 / R1 + R2 + R1 / R1 + R2 = Vmax
Or                    Vmax = R1 + R2 / R1 VR – R2 / R1 Vsat
Therefore,       Vmax – Vmin = 2R2 / R1 Vsat
and                  Vav = R1 + R2 / R1 = VR
Solving the above equations, we get
t1 = 2R2RC / R1 = Vsat
t2 = t1 = 1/2f
f = R1 / 4R2RC
The frequnency f is independent of VO, maximum frequency is limited either by slew rate or its maximum output current which determines the charging rate of C. slowest speed is limited by the bias current of op-amp.
If unequal sweep intervals t1 = t2 are desried, then VS can be changed. the positive sweep speed is given by (Vsat + VS )/ RC and the negative sweep speed is given by (Vsat – VS) / RC . the peak to peak triangular amplitude is unaffeeted by the voltage VS.
When                 VS = 0,  I = C dVC / dt
-Vsat – VS /R = – C dVOut /dt = – C. (Vmax – Vmin) /t1
Therefore,                   t1 = Vmax – Vmin / (Vsat + VS ) / RC
Or                                  t1 = 2VsatR2/R2 / (Vsat + VS) / RC
Similarly, when the output voltage of first op-amp -Vsat, then
Vsat – VS / R = – C (Vmax – Vmin / t2
Therefore,               t2 = Vmax – Vmin / (Vsat – VS) / RC
Or                              t2 = 2VsatR2/R1 / (Vsat – VS) / RC
Therefore,                 t1 / t2 = Vsat – VS / Vsat + VS
and                            t = t1 + t2
2Vsat  R2RC / R1 [2Vsat / V2sat -V2S]
The oscillation frequency is given by
f = 1 / t = R1 / 4R2RC [1 – (VS / Vsat)2]
and the duty cycle is given by
Duty cycle t1/t = V2sat – V2S / 2Vsat (Vsat + VS)
= Vsat – VS / 2Vsat = 1/2 (1 – VS / Vsat)
Example 15. (a) Consideer the pulse generator shown in figure below. in the quiescent state (before a trigger pulse is applied), find V2 , V0 and V1.
(b)   At t = 0, a narrow, positive trggering pulse V, whose magnitude exceeds VR is applied. At t = 0 +, find V0 and V1.
(c) Verify that the pulse width t = RC in (2V0)/ VR.
Sol. (a) Before a trigger pulse is applied, the circuit is in stable state with the output at V0 = + V0 (~Vz + 0.7). the capacitor C is charged with the polarity shown in figure below.
Thus,               V1 ~ 0.7 V
And                  V2 = – VR
(b) At t = 0, a narrow positive triggering pulse of higher magnitude is applied. the capacitor C voltage can not charge instantaneously. therefore, V2 becomes positiven and greater than V1 (~ 0.7 V) the comparator output changes.
Thus,                         VO = – (VZ + 0.7 V) = – V0
Since, capacitor C voltage cannot change instantaneously, therefore,
V1 = 2V0
(c) The input trigger pulse in of very short duration therefore, after the short duration pulse the voltage V2 returns to (-VR). But the output remains -V0 because V1 is – 2V0.
The capacitor now starts charging exponentially with a time constant t = RC through R towards V0, because diode is reverse biased.
VC = (-V0 – V0) (1 – e-1/RC) – V0
The voltage at point V1 is given by,
V1 = – V0 – VC
= – V0 + 2V0(1 -e-1 / RC) – V0
= 2V0e-1 / RC – t /RC
When V1 voltage becomes more than VR. the comparator output switches back to + VO let at t = T. the voltage V1 becomes – VR
– VR = – 2V0 e-T/RC
T = RC In 2VO / VR
The capacitor now starts charging towards +V0 through R untill VC reaches +V0 and V1 becomes 0.7 V.The waveform at different points are shown in figure above.
Voltage Regulators
An ideal power supply maintains a constant voltage at is output terminals under all operating condititons. the output voltage of a practical power supply changes with load generally dropping as load current increase as shown in fig. 59(a).
The terminal voltage when full load current is drawn is called full load voltage (VFL) The no load voltage is the terminal voltage when zero current is drawn from the supply, that is the open circuit terminal voltage.
Power supply performance is measured in terms of per cent voltage regulation, which indicates its ability to maintain a constant voltage it is defined as
VR = VNL – VFL / VFL x 100%
The thevenin’s equivalent of a power supply is shown in fig. 59 (b). the thevenin voltage is the no load voltage VNL and the thevenin resistance is called the output resistance R0 let the full load current be Ifl. therefore, the full load resistance Rfl is given by,
Rfl = Vfl / Ifl
From the equivalent circuit, we have
Vfl = (Rfl / Rfl + R0) Vnl
and the voltage regulation is given by
Vnl –  (Rfl / Rfl + R0)  Vnl
VR = (Rfl / Rfl + R0)  Vnl  x 100%
VR = R0 / Rfl x 100%
or           VR = R0 (Ifl / Vfl) x 100%
it is clear that the ideal power supply has zero output resistance.
Example 16. A power supply having output resistance 1.5 supplies a full load current of 500 mA to a 50 load determine,
(a) Percentage voltage regulation of the supply
(b) no load output voltage.
Sol. (a) full load output voltage
VFL = (500mA) (50) = 25 V
Therefore,   VR = R0 (IFL/VFL) x 100%
= 1. 5 (0.5 /25)x 100%
= 3.0%
(b) the no load voltage Vnl = (Rfl + R0 / Rfl) = Vfl
= 25 (50 + 1.5) / 50 = 25.75 V

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