control bus is unidirectional or bidirectional , 8085 pin Description Properties

8085 pin Description Properties control bus is unidirectional or bidirectional .

Control Bus

Control bus are various lines which have specific functions for coordinating and controlling up operations, e.g., Read/not write line, single binary digit. Control whether memory is being written to (data stored in memory) or read from (data taken out of memory) 1 = read, 0 = write. May also include clock line(s) for timing/synchronising, interrupt, reset etc. typically up has 10 control lines. It cannot function correctly without these vital control signals.

The control bus carries control signals partly unidirectional, partly bidirectional. Control signals are things like read or write. This tells memory that we are either reading from a location, specified on the Address bus or writing to a location specified. Various other signals to control and coordinate the operation of the system. Modern day microprocessors, like 80386, 80486 have much larger buses. Typically 16 or 32 bit buses which allow larger number of instructions, more memory locations, and faster arithmetic. Microcontrollers organized along same lines, except because microcontrollers have memory etc inside the chip, the buses may all the internal. In the microprocessor the three buses are external to the chip (except for the internal data bus). In case of external buses, the chip connects to the buses via buffers which are simply an electronic connection between external data bus and the internal data bus.

  1. 8085 pin Description


Single + 5 V supply

4 Vectored Interrupts (one is Non – maskable)

Serial In/Serial out port

Decimal, Binary and Double Precision Arithmetic operations.

Direct Addressing Capability of 64 kbytes of memory.

The Intel 8085 A is a new generation complete 8 bit parallel central processing unit (CPU). The 8085 A uses a multiplexed data bus. The address is split between the 8 bit address bus and the 8 bit data bus. Figures are at the end of the document.

Pin Description

The following describes the function of each pin :

A6-A 1s (Output 3 state)

Address bus, the most significant 8 bit of the memory address or the 8-bit of the I/O address, tri stated during hold and halt modes.

AD0-7 (Input/Output 3 state)

Multiplexed Address/Data bus. Lower 8-bit of the memory address (or I/O address) appear on the bus during the first clock cycle of a machine state. It then becomes the data bus during the second and third clock cycles. Tri stated during hold and halt modes.

ALE (Output)

Address latch enable; it occurs during the first clock cycle of a machine state and enable the address to get latched into the on chip latch of peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information. ALE can also be used to strobe the status information. ALE is never tri stated.

S0, S1 (Output)

Data bus status. Encoded status of the bus cycle:

SI     S0

0      0             HALT

0      1            WRITE

1      0          READ

1      1           FETCH

SI can be used as an advanced R/W status.

RD (Output 3 state)

READ, indicates the selected memory or I/O devices is to be read and that the data bus is available for the data transfer.

WR (output 3 state)

WRITE; indicates the data on the data bus is to be written into the selected memory or I/O location. Data is setup at the trailing edge of WR, 3 stated during hold and halt modes.

READT (Input)

If ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If ready is low, the CPU will wait for ready to go high before completing the read or write cycle.

HOLD (Input)

HOLD, indicates that another master is requesting the use of the address and data bus. The CPU, upon receiving the HOLD request will relinquish the use of buses as soon as the completion of the current machine cycle. Internal processing can continue.

The processor can regain the buses only after the hold is removed. When the hold is acknowledged, the address, data, RD, WR, and IO/M lines are 3 stated.

HLDA (Output)

HLDA ACKNOWLEDGE, indicates that the CPU has received the hold request and that it will relinquish the buses in the next clock cycle. HLDA goes low after the hold request is removed. The CPU takes the buses one half clock cycle after HLDA goes low.

INTR (Input)

INTERRUPT REQUEST, is used as general purpose interrupt. It is sampled only during the next to the last clock of the instruction. If it is active, the program counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by reset and immediately after an interrupt is accepted.

INTA (Output)

INTERRUPT ACKNOWLEDGE, is used instead of (and has the same timing as) RD during the instruction cycle after an INTR is accepted. It can be used to activate the 8259 Interrupt chip or some other interrupt port.

RST  5.5

RST  6.5 (Inputs)

RST  7.5

RESTART INTERRUPTS, There three inputs have the same timing as INTR except they cause an internal RESTART to be automatically inserted.

RST 7.5  Highest priority

RST 6.5

RST 5.5  lowest priority

The priority of these interrupts is ordered as shown above. These interrupts have a higher priority than the INTR.

TRAP (Input)

Trap interrupt is a non-maskable restart interrupt. It is recognized at the same time as INTR. It is unaffected by any mask or interrupt enable. It has the highest priority of any interrupt.

RESET IN (Input)

Reset sets the program counter to zero and resets the interrupt enable and HLDA flip-flops. None of the other flags or registers (except the instruction register) are affected. The CPU is held in the reset condition as long as reset is applied.

RESET OUT (Output)

Indicates CPU is being reset. It can be used as a system RESET. The signal is synchronized to the processor clock.

X1, X2 (Input)

Crystal or R/C network connections to set the internal clock generator X1 can also be an external clock input instead of a crystal. The input frequency is divided by 2 to give the internal operating frequency.

CLK (Output)

Clock output for use a system clock when a crystal or R/C network is used as an input to the CPU. The period of CLK is twice the X1, X2 input period.

IO/M (Output)

IO/M indicates whether the read/write is to memory or I/O Tristated during hold and halt moves.

SID (Input)

Serial input data line. The data on this line is loaded into accumulator bit-7 whenever a RIM instruction is executed.

SOD (Output)

Serial output data line. The output SOD is set or reset as specified by the SIM instruction.

VCC : +5 V supply

VSS : Ground Reference.

  1. 8085 Functional Description

The 8085 A is a complete 8 bit parallel central processor. It requires a single +5 v supply. Its basic clock speed is 3 MHz thus improving on the present 8080 s performance with higher system speed. Also it is designed to fit into a minimum system of three ICs. The CPU, a RAM/IO and a ROM or PROM/IO chip.

The 8085A uses a multiplexed data bus. The address is split between the higher 8-bit address bus and the lower 8-bit address/data bus. During the first cycle, the address is sent out. The lower 8 bit are latched into the peripherals by the address latch enable (ALE). During the rest of the machine cycle, the data bus is used for memory of I/O data.

The 8085 A provides RD, WR and IO/Memory signals for bus control. An interrupt acknowledge signal (INTA) is also provided. HOLD, READY and all interrupts are synchronized. The 8085A also provides serial input data (SID) and serial output data (SOD) lines for simple serial interface.

In addition to these features, the 8085 A has three maskable restart interrupts and one non-maskable TRAP interrupt. The 8085 A provides RD, WR and IO/M signals for bus control.

Status Information

Status information is directly available from the 8085 – A, ALE serves as a status strobe. The status is partially encoded and provides the user with advanced timing of the type of bus transfer being done. IO/M cycle status signal is provided directly also. Decoded S0, S1 carry the following status information.

Halt, write, Read, Fetch

S1 can be interpreted as R/W in all bus transfers. In the 8085 A, the 8 LSB of address are multiplexed with the data instead of status. The ALE line is used as a strobe to enter the lower half of the address into the memory or peripheral address latch. This also frees extra pins for expanded interrupt capability.

Interrupt and Serial I/O

The 8085 A has 5 interrupt inputs: INTR, RST 5.5, RST 6.5, RST 7.5 and TRAP. INTR is identical in function to the 8080 INT. Each of the three RESTART inputs, 5.5, 6.5, 7.5 has a programmable mask. TRAP is also a RESTART interrupt except it is non-maskable.

The three RESTART interrupts cause the internal execution of RST (saving the program counter in the stack and branching to the RESTART address) if the interrupts are enabled and if the interrupt mask is not set. The non-maskable TRAP causes the internal execution of a RST independent of the state of the interrupt enable or masks.

The interrupts are arranged in a fixed priority that determines which interrupt is to be recognized if more than one is pending as follows; TRAP highest priority , RST 7.5, RST 6.5, RST 5.5 INTR Lowest priority. This priority scheme does not take into account the priority of a routine that was started by a higher priority interrupt. RST 5.5 can interrupt a RST 7.5 routine if the interrupts were re-enable before the end of the RST 7.5 routine. The TRAP interrupt is useful for catastrophic errors such as power failure or bus error. The TRAP input is recognized just as any other interrupt but has the highest priority. It is not affected by any flag or mask. The TRAP input is both edge and level sensitive.

Basic System Timing

The 8085 A has a multiplexed data bus. ALE is used as a strobe to sample the lower 8 bit of address on the data bus, figure shows an instruction fetch, memory read and I/O write cycle (OUT). Note that during the I/O write and read cycle  that the I/O port address is copied on both the upper and lower half of the address. As in 8080, the READY line is used to extend the read and write pulse lengths so that the 8085 A can be used with slow memory. Hold causes the CPU to relinquish the bus when it is through with it by floating the address and data buses.

System Interface

8085 A family includes memory components which are directly compatible to the 8085 A CPU. For example, a system consisting of the three chips, 8085 A, 8156 and 8355 will have the following features:

2 kbytes ROM

256 byte RAM

One Timer/Counter

Four interrupt levels

Serial in/serial out ports

In addition to standard I/O, the memory mapped I/O offers an efficient I/O addressing technique. With this technique, an area of memory address space is assigned for I/O address, thereby, using the memory address for I/O manipulation. The 8085 A CPU can also interface with the standard memory that does not have the multiplexed address/data bus.